-
1
-
-
48649091785
-
High performance CMOS variability in the 65 nm regime and beyond
-
S. Nassif, K. Bernstein, D. Frank, A. Gattiker, W. Haensch, B. L. Ji, E. Nowak, D. Pearson, and N. J. Rohrer, "High performance CMOS variability in the 65 nm regime and beyond," in IEDM Tech. Dig., 2007, pp. 569-571.
-
(2007)
IEDM Tech. Dig.
, pp. 569-571
-
-
Nassif, S.1
Bernstein, K.2
Frank, D.3
Gattiker, A.4
Haensch, W.5
Ji, B.L.6
Nowak D, E.7
Pearson, D.8
Rohrer, N.J.9
-
2
-
-
64549110647
-
Advanced simulation of statistical variability and reliability in nano CMOS transistors
-
A. Asenov, S. Roy, R. A. Brown, G. Roy, C. Alexander, C. Riddet, C. Millar, B. Cheng, A. Martinez, N. Seoane, D. Reid, M. F. Bukhori, X. Wang, and U. Kovac, "Advanced simulation of statistical variability and reliability in nano CMOS transistors," in IEDM Tech. Dig., 2008, p. 421.
-
(2008)
IEDM Tech. Dig.
, pp. 421
-
-
Asenov, A.1
Roy, S.2
Brown, R.A.3
Roy, G.4
Alexander, C.5
Riddet, C.6
Millar, C.7
Cheng, B.8
Martinez, A.9
Seoane, N.10
Reid, D.11
Bukhori, M.F.12
Wang, X.13
Kovac, U.14
-
3
-
-
64549133760
-
High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding
-
O. Weber, O. Faynot, F. Andrieu, C. Buj-Dufournet, F. Allain, P. Scheiblin, J. Foucher, N. Daval, D. Lafond, L. Tosti, L. Brevard, O. Rozeau, C. Fenouillet-Beranger, M. Marin, F. Boeuf, D. Delprat, K. Bourdelle, B.-Y. Nguyen, and S. Deleonibus, "High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding," in IEDM Tech. Dig., 2008, pp. 245-248.
-
(2008)
IEDM Tech. Dig.
, pp. 245-248
-
-
Weber, O.1
Faynot, O.2
Andrieu, F.3
Buj-Dufournet, C.4
Allain, F.5
Scheiblin, P.6
Foucher, J.7
Daval, N.8
Lafond, D.9
Tosti, L.10
Brevard, L.11
Rozeau, O.12
Fenouillet-Beranger, C.13
Marin, M.14
Boeuf, F.15
Delprat, D.16
Bourdelle, K.17
Nguyen, B.-Y.18
Deleonibus, S.19
-
4
-
-
77955596816
-
Extremely thin SOI CMOS with record low variability for LP-SoC applications
-
K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, D. Shahrjerdi, L. F. Edge, A. Kimball, S. Kanakasabapathy, K. Xiu, S. Schmitz, A. Reznicek, T. Adam, H. He, N. Loubet, S. Holmes, S. Mehta, D. Yang, A. Upham, S.-C. Seo, J. L. Herman, R. Johnson, Y. Zhu, P. Jamison, B. S. Haran, Z. Zhu, L. H. Vanamurth, S. Fan, D. Horak, H. Bu, P. J. Oldiges, D. K. Sadana, D. McHerron, J. O'Neill, and B. Doris, "Extremely thin SOI CMOS with record low variability for LP-SoC applications," in IEDM Tech. Dig., 2009, pp. 49-52.
-
(2009)
IEDM Tech. Dig.
, pp. 49-52
-
-
Cheng, K.1
Khakifirooz, A.2
Kulkarni, P.3
Ponoth, S.4
Kuss, J.5
Shahrjerdi, D.6
Edge, L.F.7
Kimball, A.8
Kanakasabapathy, S.9
Xiu, K.10
Schmitz, S.11
Reznicek, A.12
Adam, T.13
He, H.14
Loubet, N.15
Holmes, S.16
Mehta, S.17
Yang, D.18
Upham, A.19
Seo, S.-C.20
Herman, J.L.21
Johnson, R.22
Zhu, Y.23
Jamison, P.24
Haran, B.S.25
Zhu, Z.26
Vanamurth, L.H.27
Fan, S.28
Horak, D.29
Bu, H.30
Oldiges, P.J.31
Sadana, D.K.32
McHerron, D.33
O'Neill, J.34
Doris, B.35
more..
-
5
-
-
79958067941
-
Planar FDSOI technology: A powerful architecture for the 20 nm node and beyond
-
O. Faynot, F. Andrieu, O. Weber, C. Fenouillet-Béranger, P. Perreau, J. Mazurier, T. Benoist, O. Rozeau, T. Poiroux, M. Vinet, L. Grenouillet, J.-P. Noel, N. Posseme, S. Barnola, F. Martin, C. Lapeyre, M. Cassé, X. Garros, M.-A. Jaud, O. Thomas, G. Cibrario, L. Tosti, L. Brevard, C. Tabone, P. Gaud, S. Barraud, T. Ernst, and S. Deleonibus, "Planar FDSOI technology: A powerful architecture for the 20 nm node and beyond," in IEDM Tech. Dig., 2010, pp. 321-324.
-
(2010)
IEDM Tech. Dig.
, pp. 321-324
-
-
Faynot, O.1
Andrieu, F.2
Weber, O.3
Fenouillet-Béranger, C.4
Perreau, P.5
Mazurier, J.6
Benoist, T.7
Rozeau, O.8
Poiroux, T.9
Vinet, M.10
Grenouillet, L.11
Noel, J.-P.12
Posseme, N.13
Barnola, S.14
Martin, F.15
Lapeyre, C.16
Cassé, M.17
Garros, X.18
Jaud, M.-A.19
Thomas, O.20
Cibrario, G.21
Tosti, L.22
Brevard, L.23
Tabone, C.24
Gaud, P.25
Barraud, S.26
Ernst, T.27
Deleonibus, S.28
more..
-
6
-
-
34547781729
-
Impact of parameter variations and RDF on short-channel FD-SOI MOSFETS with extremely thin box
-
Aug.
-
T. Ohtou, N. Sugii, and T. Hiramoto, "Impact of parameter variations and RDF on short-channel FD-SOI MOSFETS with extremely thin box," IEEE Electron Device Lett., vol. 28, no. 8, pp. 740-743, Aug. 2007.
-
(2007)
IEEE Electron Device Lett.
, vol.28
, Issue.8
, pp. 740-743
-
-
Ohtou, T.1
Sugii, N.2
Hiramoto, T.3
-
7
-
-
74349085488
-
Impact of additional factors in VTH variability of metal-high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates
-
K. Ohmori, T. Matsuki, D. Ishikawa, T. Morooka, T. Aminaka, Y. Sugita, T. Chikyow, K. Shiraishi, Y. Nara, and K. Yamada, "Impact of additional factors in VTH variability of metal-high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates," in IEDM Tech. Dig., 2008, pp. 409-412.
-
(2008)
IEDM Tech. Dig.
, pp. 409-412
-
-
Ohmori, K.1
Matsuki, T.2
Ishikawa, D.3
Morooka, T.4
Aminaka, T.5
Sugita, Y.6
Chikyow, T.7
Shiraishi, K.8
Nara, Y.9
Yamada, K.10
-
8
-
-
13344275832
-
Narrow-width SOI devices: The role of quantum-mechanical size quantization effect and unintentional doping the device operation
-
DOI 10.1109/TED.2004.842715
-
D. Vasileska and S. Ahmed, "Narrow-width SOI devices: The role of quantum-mechanical size quantization effect and unintentional doping on the device operation," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 227-236, Feb. 2005. (Pubitemid 40195970)
-
(2005)
IEEE Transactions on Electron Devices
, vol.52
, Issue.2
, pp. 227-236
-
-
Vasileska, D.1
Ahmed, S.S.2
-
9
-
-
77957862598
-
Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method
-
T. Tsunomura, A. Kumar, T. Mizutani, C. Lee, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami, "Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method," in Proc. VLSI Tech. Symp., 2010, pp. 97-98.
-
(2010)
Proc. VLSI Tech. Symp.
, pp. 97-98
-
-
Tsunomura, T.1
Kumar, A.2
Mizutani, T.3
Lee, C.4
Nishida, A.5
Takeuchi, K.6
Inaba, S.7
Kamohara, S.8
Terada, K.9
Hiramoto, T.10
Mogami, T.11
-
10
-
-
78650579761
-
Suppression of DIBL and current-onset voltage variability in intrinsic channel FD-SOI MOSFETs
-
T. Hiramoto, T. Mizutani, A. Kumar, A. Nishida, T. Tsunomura, S. Inaba, K. Takeuchi, S. Kamohara, and T. Mogami, "Suppression of DIBL and current-onset voltage variability in intrinsic channel FD-SOI MOSFETs," in Proc. Int. SOI Conf., 2010, pp. 1-2.
-
(2010)
Proc. Int. SOI Conf.
, pp. 1-2
-
-
Hiramoto, T.1
Mizutani, T.2
Kumar, A.3
Nishida, A.4
Tsunomura, T.5
Inaba, S.6
Takeuchi, K.7
Kamohara, S.8
Mogami, T.9
-
11
-
-
0036923355
-
The effective drive current in CMOS inverters
-
M. H. Na, E. J. Nowak, W. Haensch, and J. Cai, "The effective drive current in CMOS inverters," in IEDM Tech. Dig., 2002, pp. 121-124.
-
(2002)
IEDM Tech. Dig.
, pp. 121-124
-
-
Na, M.H.1
Nowak, E.J.2
Haensch, W.3
Cai, J.4
-
12
-
-
84857453584
-
-
Gold Standard Simulations Ltd
-
Gold Standard Simulations Ltd., www.goldstandardsimulations.com/
-
-
-
-
13
-
-
33947265310
-
Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs
-
Dec.
-
G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3063-3070, Dec. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.12
, pp. 3063-3070
-
-
Roy, G.1
Brown, A.R.2
Adamu-Lema, F.3
Roy, S.4
Asenov, A.5
-
14
-
-
83455236938
-
-
Dec. European Commission FP6 Integr. Proj. PULLNANO (IST-026828) Deliverable D-6451
-
M. Agostinelli, P. Palestri, L. Selmi, M. Panozzo, C. Fiegna, A. Schenk et al., Definition of Template Devices, Dec. 2007, European Commission FP6 Integr. Proj. PULLNANO (IST-026828) Deliverable D-6451.
-
(2007)
Definition of Template Devices
-
-
Agostinelli, M.1
Palestri, P.2
Selmi, L.3
Panozzo, M.4
Fiegna, C.5
Schenk, A.6
-
15
-
-
79960898583
-
A simple series resistance extraction methodology for advanced CMOS devices
-
Aug.
-
J. Campbell, K. Cheung, J. Suehle, and A. Oates, "A simple series resistance extraction methodology for advanced CMOS devices," IEEE Electron Device Lett., vol. 32, no. 8, pp. 1047-1049, Aug. 2011.
-
(2011)
IEEE Electron Device Lett.
, vol.32
, Issue.8
, pp. 1047-1049
-
-
Campbell, J.1
Cheung, K.2
Suehle, J.3
Oates, A.4
|