From instruction traces to specialized reconfigurable arrays

Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

Volumn , Issue , 2011, Pages 386-391

  Bispo, João ^a   Paulino, Nuno ^b   Cardoso, João M P ^b   Ferreira, João Canas ^c  

^a INSTITUTO SUPERIOR TÉCNICO   (Portugal)

^b UNIVERSITY OF PORTO   (Portugal)

^c UNIVERSITY OF PORTO   (Portugal)

Author keywords

Binary Translation; Graph Mapping; Hardware Accelerator; Instruction Trace; Megablock; Reconfigurable Computing

Indexed keywords

BINARY TRANSLATION; HARDWARE ACCELERATOR; INSTRUCTION TRACE; MEGABLOCK; RECONFIGURABLE COMPUTING;

RECONFIGURABLE ARCHITECTURES;

EID: 84856871920     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReConFig.2011.43     Document Type: Conference Paper

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