-
1
-
-
78650034452
-
Low-voltage tunnel transistors for beyond CMOS logic
-
Dec.
-
A. C. Seabaugh and Q. Zhang, "Low-voltage tunnel transistors for beyond CMOS logic," Proc. IEEE, vol. 98, no. 12, pp. 2095-2110, Dec. 2010.
-
(2010)
Proc. IEEE
, vol.98
, Issue.12
, pp. 2095-2110
-
-
Seabaugh, A.C.1
Zhang, Q.2
-
2
-
-
79957617091
-
Stepped broken-gap heterobarrier tunneling field-effect transistor for ultralow power and high speed
-
Jun.
-
L. F. Register, M. M. Hasan, and S. K. Banerjee, "Stepped broken-gap heterobarrier tunneling field-effect transistor for ultralow power and high speed," IEEE Electron Device Lett., vol. 32, no. 6, pp. 743-745, Jun. 2011.
-
(2011)
IEEE Electron Device Lett.
, vol.32
, Issue.6
, pp. 743-745
-
-
Register, L.F.1
Hasan, M.M.2
Banerjee, S.K.3
-
3
-
-
64549108830
-
Doublegate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and 〈 60 mV/dec subthreshold slope
-
T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, "Doublegate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and 〈 60 mV/dec subthreshold slope," in IEDM Tech. Dig., 2008, pp. 947-949.
-
(2008)
IEDM Tech. Dig.
, pp. 947-949
-
-
Krishnamohan, T.1
Kim, D.2
Raghunathan, S.3
Saraswat, K.4
-
4
-
-
33646179633
-
Two sub-band conductivity of Si quantum well
-
May SPEC. ISS
-
M. Prunnila and J. Ahopelto, "Two sub-band conductivity of Si quantum well," Phys. E, Low-Dimensional Syst. Nanostruct., vol. 32, no. 1/2, pp. 281-284, May 2006, SPEC. ISS.
-
(2006)
Phys. E, Low-Dimensional Syst. Nanostruct.
, vol.32
, Issue.1-2
, pp. 281-284
-
-
Prunnila, M.1
Ahopelto, J.2
-
5
-
-
52349103660
-
Electrons and holes in Si quantum well: A room-temperature transport and drag resistance study
-
Sep.
-
M. Prunnila, S. J. Laakso, J. M. Kivioja, and J. Ahopelto, "Electrons and holes in Si quantum well: A room-temperature transport and drag resistance study," Appl. Phys. Lett., vol. 93, no. 11, p. 112113, Sep. 2008.
-
(2008)
Appl. Phys. Lett.
, vol.93
, Issue.11
, pp. 112113
-
-
Prunnila, M.1
Laakso, S.J.2
Kivioja, J.M.3
Ahopelto, J.4
-
6
-
-
82955201869
-
Electron-hole bilayer tunnel FET for steep subthreshold swing and improved on current
-
L. Lattanzio, L. De Michielis, and A. M. Ionescu, "Electron-hole bilayer tunnel FET for steep subthreshold swing and improved ON current," in Proc. ESSDERC, 2011, pp. 259-262.
-
(2011)
Proc. ESSDERC
, pp. 259-262
-
-
Lattanzio, L.1
De Michielis, L.2
Ionescu, A.M.3
-
7
-
-
72049110509
-
Ultralow-voltage bilayer graphene tunnel FET
-
Oct.
-
G. Fiori and G. Iannaccone, "Ultralow-voltage bilayer graphene tunnel FET," IEEE Electron Device Lett., vol. 30, no. 10, pp. 1096-1098, Oct. 2009.
-
(2009)
IEEE Electron Device Lett.
, vol.30
, Issue.10
, pp. 1096-1098
-
-
Fiori, G.1
Iannaccone, G.2
-
8
-
-
77954213627
-
Ultrahigh aspect-ratio FinFET technology
-
V. Jovanovíc, T. Suligoj, M. Poljak, Y. Civale, and L. K. Nanver, "Ultrahigh aspect-ratio FinFET technology," Solid-State Electron., vol. 54, no. 9, pp. 870-876, 2010.
-
Solid-State Electron.
, vol.54
, Issue.9
, pp. 870-876
-
-
Jovanovíc, V.1
Suligoj, T.2
Poljak, M.3
Civale, Y.4
Nanver, L.K.5
-
9
-
-
79953058995
-
Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing (≤ 50 mV/decade) at room temperature
-
Apr.
-
R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, "Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing (≤ 50 mV/decade) at room temperature," IEEE Electron Device Lett., vol. 32, no. 4, pp. 437-439, Apr. 2011.
-
(2011)
IEEE Electron Device Lett.
, vol.32
, Issue.4
, pp. 437-439
-
-
Gandhi, R.1
Chen, Z.2
Singh, N.3
Banerjee, K.4
Lee, S.5
-
11
-
-
0002930518
-
Theory of tunneling
-
Jan.
-
E. O. Kane, "Theory of tunneling," J. Appl. Phys., vol. 32, no. 1, pp. 83-91, Jan. 1961.
-
(1961)
J. Appl. Phys.
, vol.32
, Issue.1
, pp. 83-91
-
-
Kane, E.O.1
-
12
-
-
0000776042
-
Macroscopic physics of the silicon inversion layer
-
May
-
M. G. Ancona and H. F. Tiersten, "Macroscopic physics of the silicon inversion layer," Phys. Rev. B, Condens. Matter Mater. Phys., vol. 35, no. 15, pp. 7959-7965, May 1987.
-
(1987)
Phys. Rev. B, Condens. Matter Mater. Phys.
, vol.35
, Issue.15
, pp. 7959-7965
-
-
Ancona, M.G.1
Tiersten, H.F.2
-
13
-
-
79551640976
-
A binary tunnel field effect transistor with a steep sub-threshold swing and increased on current
-
Dec.
-
R. Asra, K. V. R. M. Murali, and V. R. Rao, "A binary tunnel field effect transistor with a steep sub-threshold swing and increased on current," Jpn. J. Appl. Phys., vol. 49, no. 12, p. 120203, Dec. 2010.
-
(2010)
Jpn. J. Appl. Phys.
, vol.49
, Issue.12
, pp. 120203
-
-
Asra, R.1
Murali, K.V.R.M.2
Rao, V.R.3
-
14
-
-
54849404161
-
Tunneling phenomena in carbon nanotube field-effect transistors
-
Applications and Materials
-
J. Knoch and J. Appenzeller, "Tunneling phenomena in carbon nanotube field-effect transistors," Phys. Stat. Sol. (A), vol. 205, no. 4, pp. 679-694, 2008, Applications and Materials.
-
(2008)
Phys. Stat. Sol. (A)
, vol.205
, Issue.4
, pp. 679-694
-
-
Knoch, J.1
Appenzeller, J.2
-
15
-
-
69749099372
-
Effective capacitance and drive current for tunnel FET (TFET) CV/I estimation
-
Sep.
-
S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, "Effective capacitance and drive current for tunnel FET (TFET) CV/I estimation," IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 2092-2098, Sep. 2009.
-
(2009)
IEEE Trans. Electron Devices
, vol.56
, Issue.9
, pp. 2092-2098
-
-
Mookerjea, S.1
Krishnan, R.2
Datta, S.3
Narayanan, V.4
-
16
-
-
80052647584
-
Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic
-
U. E. Avci, R. Rios, K. Kuhn, and I. A. Young, "Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic," in VLSI Symp. Tech. Dig., 2011, pp. 124-125.
-
(2011)
VLSI Symp. Tech. Dig.
, pp. 124-125
-
-
Avci, U.E.1
Rios, R.2
Kuhn, K.3
Young, I.A.4
|