Fault models for logic circuits in the multigate era

IEEE Transactions on Nanotechnology

Volumn 11, Issue 1, 2012, Pages 182-193

  Bhoj, Ajay N ^a   Simsir, Muzaffer O ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

Device simulation; fault models; FinFETs; independent gate structure; leakage; shorted gate structure

Indexed keywords

BACK GATES; BACK-GATE; CIRCUIT TESTING; DELAY FAULT TEST; DEVICE SIMULATIONS; ELECTROSTATIC INTEGRITY; FABRICATION PROCESS; FAULT MODEL; FINFET DEVICES; FINFETS; MIXED MODE; MULTI-GATE FETS; PULSE BROADENING; PULSE SHRINKING; SINGLE FAULT; TECHNOLOGY NODES;

GATES (TRANSISTOR); INTEGRATED CIRCUITS; LEAKAGE (FLUID); MESFET DEVICES; RANDOM ACCESS STORAGE;

LOGIC CIRCUITS;

EID: 84855705052     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2011.2169807     Document Type: Article

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