-
1
-
-
35448984859
-
-
Sept Xilinx, Inc
-
Xilinx Floating-Point Operator v3.0, Xilinx, Inc., http://www.xilinx.com/ support/documentation/ip-documentation/floating-point-ds335.pdf, Sept. 2006.
-
(2006)
Xilinx Floating-Point Operator v3.0
-
-
-
2
-
-
74849104613
-
An improved reduction algorithm with deeply pipelined operators
-
Oct
-
Y.-G. Tai, C.-T. D. Lo, and K. Psarris, "An Improved Reduction Algorithm with Deeply Pipelined Operators," Proc. IEEE Int'l Conf. Systems, Man and Cybernetics (SMC '09), pp. 3060-3065, Oct. 2009.
-
(2009)
Proc. IEEE Int'l Conf. Systems, Man and Cybernetics (SMC '09)
, pp. 3060-3065
-
-
Tai, Y.-G.1
Lo, C.-T.D.2
Psarris, K.3
-
5
-
-
0022054523
-
Vector-reduction techniques for arithmetic pipelines
-
May
-
L.M. Ni and K. Hwang, "Vector-Reduction Techniques for Arithmetic Pipelines," IEEE Trans. Computer, vol. C-34, no. 5, pp. 404-411, May 1985.
-
(1985)
IEEE Trans. Computer
, vol.C-34
, Issue.5
, pp. 404-411
-
-
Ni, L.M.1
Hwang, K.2
-
6
-
-
0026104540
-
An improved vector-reduction method
-
Feb
-
H. Sips and H. Lin, "An Improved Vector-Reduction Method," IEEE Trans. Computer, vol. 40, no. 2, pp. 214-217, Feb. 1991.
-
(1991)
IEEE Trans. Computer
, vol.40
, Issue.2
, pp. 214-217
-
-
Sips, H.1
Lin, H.2
-
7
-
-
34147131364
-
A hybrid approach for mapping conjugate gradient onto an FPGA-augmented reconfigurable supercomputer
-
DOI 10.1109/FCCM.2006.8, 4020890, Proceedings - 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2006
-
G.R. Morris, V.K. Prasanna, and R.D. Anderson, "A Hybrid Approach for Mapping Conjugate Gradient onto an FPGAAugmented Reconfigurable Supercomputer," Proc. 14th Ann. IEEE Symp. Field-Programmable Custom Computing Machines (FCCM '06), pp. 3-12, 2006. (Pubitemid 47159821)
-
(2006)
Proceedings - 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2006
, pp. 3-12
-
-
Morris, G.R.1
Prasanna, V.K.2
Anderson, R.D.3
-
8
-
-
34547415470
-
An FPGA-based application-specific processor for efficient reduction of multiple variable-length floating-point data sets
-
DOI 10.1109/ASAP.2006.11, 4019536, Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
-
G.R. Morris, V.K. Prasanna, and R.D. Anderson, "An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets," Proc. 17th IEEE Int'l Conf. Application-Specific Systems, Architectures and Processors (ASAP '06), pp. 323-330, 2006. (Pubitemid 47158351)
-
(2006)
Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
, pp. 323-330
-
-
Morris, G.R.1
Prasanna, V.K.2
Anderson, R.D.3
-
12
-
-
34648814129
-
High-performance reduction circuits using deeply pipelined operators on FPGAs
-
DOI 10.1109/TPDS.2007.1068
-
L. Zhuo, G.R. Morris, and V.K. Prasanna, "High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs," IEEE Trans. Parallel Distributed Systems, vol. 18, no. 10, pp. 1377-1392, Oct. 2007. (Pubitemid 47456003)
-
(2007)
IEEE Transactions on Parallel and Distributed Systems
, vol.18
, Issue.10
, pp. 1377-1392
-
-
Zhou, L.1
Morris, G.R.2
Prasanna, V.K.3
-
15
-
-
17644368925
-
Parallel out-of-core computation and updating of the QR factorization
-
DOI 10.1145/1055531.1055534
-
B.C. Gunter and R.A.V.D. Geijn, "Parallel Out-of-Core Computation and Updating of the QR Factorization," ACM Trans. Math. Software, vol. 31, no. 1, pp. 60-78, 2005. (Pubitemid 40557862)
-
(2005)
ACM Transactions on Mathematical Software
, vol.31
, Issue.1
, pp. 60-78
-
-
Gunter, B.C.1
Van De Geijn, R.A.2
-
16
-
-
51049083291
-
-
technical report, LAPack Working Notes #190
-
A. Buttari, J. Langou, J. Kurzak, and J. Dongarra, "Parallel Tiled QR Factorization For Multicore Architectures," technical report, LAPack Working Notes #190, http://www.netlib.org/lapack/lawnspdf/lawn190.pdf, 2007.
-
(2007)
Parallel Tiled QR Factorization for Multicore Architectures
-
-
Buttari, A.1
Langou, J.2
Kurzak, J.3
Dongarra, J.4
-
17
-
-
79551512963
-
-
technical report, LAPack Working Notes #222, Innovative Computing Laboratory, Univ. of Tennessee
-
B. Hadri, H. Ltaief, E. Agullo, and J. Dongarra, "Enhancing Parallelism of Tile QR Factorization for Multicore Architectures," technical report, LAPack Working Notes #222, Innovative Computing Laboratory, Univ. of Tennessee, http://www.netlib.org/lapack/lawnspdf/lawn222.pdf, 2009.
-
(2009)
Enhancing Parallelism of Tile QR Factorization for Multicore Architectures
-
-
Hadri, B.1
Ltaief, H.2
Agullo, E.3
Dongarra, J.4
-
19
-
-
30344436225
-
-
Xilinx, Inc
-
Virtex-4 Family Overview, Xilinx, Inc., http://www.xilinx.com/support/ documentation/data-sheets/ds112.pdf, 2007.
-
(2007)
Virtex-4 Family Overview
-
-
-
20
-
-
62949240224
-
-
Xilinx, Inc
-
Virtex-5 Family Overview, Xilinx, Inc., http://www.xilinx.com/support/ documentation/data-sheets/ds100.pdf, 2009.
-
(2009)
Virtex-5 Family Overview
-
-
|