High-performance and area-efficient reduction circuits on FPGAs

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn , Issue , 2005, Pages 52-59

  Zhuo, Ling ^a   Prasanna, Viktor K ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; MATRIX ALGEBRA; VECTORS;

DATA HAZARDS; FLOATING-POINT UNITS; REDUCTION CIRCUIT;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33847218692     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CAHPC.2005.28     Document Type: Conference Paper

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