An FPGA-based application-specific processor for efficient reduction of multiple variable-length floating-point data sets

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2006, Pages 323-330

  Morris, Gerald R ^a   Prasanna, Viktor K ^a   Anderson, Richard D ^b  

^a University of Southern California ^*  (United States)

^b Major Shared Resource Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH-LEVEL LANGUAGE (HLL); RECONFIGURABLE COMPUTERS (RCS); SPARSE MATRIX; VARIABLE-LENGTH FLOATING-POINT;

COMPUTER SOFTWARE; DATA REDUCTION; DATA STRUCTURES; ITERATIVE METHODS; SCHEDULING ALGORITHMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34547415470     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2006.11     Document Type: Conference Paper

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