Designing scalable FPGA-based reduction circuits using pipelined floating-point cores

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Zhuo, Ling ^a   Morris, Gerald R ^a   Prasanna, Viktor K ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA HAZARDS; FLOATING-POINT CORES; MEMORY BANDWIDTH; SCALABILITY;

BANDWIDTH; COMPUTATIONAL METHODS; DIGITAL ARITHMETIC; NETWORKS (CIRCUITS); PIPELINE PROCESSING SYSTEMS; PROBLEM SOLVING; STORAGE ALLOCATION (COMPUTER);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746284911     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.165     Document Type: Conference Paper

References (15)

1. Altera Corporation, http://www.altera.com/.
2. N. W. Bergmann and J. A. Williams. The Egret platform for reconfigurable System-on-Chip. In Proceedings of the IEEE International Conference on Field-Programmable Technology, pages 340-343, Tokyo, December 2003.
3. Cray Inc. Cray XD1™. http://www.cray.com/products/xd1/.
4. W. Fithian, S. Brown, R. Singleterry, and O. Storaasli. Iterative matrix equation solver for a reconfigurable FPGA-based hypercomputer. http://www.starbridgesystems.com/resources/publications, September 2003.
5. G. Govindu, L. Zhuo, S. Choi, and V. K. Prasanna. Analysis of high-performance floating-point arithmetic on FPGAs. In Proceedings of the 11th Reconfigurable Architectures Workshop, Santa Fe, NM, April 2004.
6. M. Leeser and X. Wang. Variable precision floating-point division and square root. In Proceedings of the 8th Annual. High Performance Embedded Computing Workshop, HPEC 2004, pages 47-48, Lexington, MA, September 2004.
7. Z. Luo and M. Martonosi. Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques. IEEE Transactions of Computers, 49(3):208-218, March 2000.
8. P. Lysaght and D. Levi. Of gates and wires. In Proceedings of the 18th International Parallel and Distributed Processing Symposium, page 132, Santa Fe, NM, April 2004.
9. U. Malik, K. So, and O. Diessel. Resource-aware run-time elaboration of behavioural FPGA specifications. In Proceedings of the IEEE International Conference on Field-Programmable Technology, pages 68-75, Hong Kong, December 2002.
10. R. Scrofano and V. K. Prasanna. Computing Lennard-Jones potentials and forces with reconfigurable hardware. In Proceedings of the Interational Conference on Engineering Reconflgurable Systems and Algorithms, pages 284-290, Las Vegas, NV, June 2004.
11. SRC Computers. MAPstation™. http://www.srccomp.com/MAPstations.htm.
12. K. D. Underwood and K. S. Hemmert. Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance. In Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, April 2004.
13. Xilinx Inc. http://www.xilinx.com.
14. L. Zhuo and V. K. Prasanna. Design Tradeoffs for BLAS Operations on Reconfigurable Hardware. submitted to the 34th International Conference on Parallel Processing, 2005.
15. L. Zhuo and V. K. Prasanna. Sparse Matrix-Vector Multiplication on FPGAs. In Proceedings of the 13th ACM International Symposium on Field-Programmable Gate Arrays, Montery, California, February 2005.