High-performance FPGA-based general reduction methods

Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005

Volumn 2005, Issue , 2005, Pages 323-324

  Morris, Gerald R ^a   Zhuo, Ling ^a   Prasanna, Viktor K ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER REQUIREMENTS; FLOATING-POINT KERNELS; GENERAL-PURPOSE PROCESSORS;

ALGORITHMS; BUFFER STORAGE; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; PERFORMANCE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746169464     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2005.42     Document Type: Conference Paper

References (2)

1. L. M. Ni and K. Hwang. Vector reduction methods for arithmetic pipelines. In Proceedings of the 6th International Symposium on Computer Arithmetic, June 1983.
2. L. Zhuo, G. R. Morris, and V. K. Prasanna. Designing scalable FPGA-based reduction circuits using pipelined floating-point cores. In Proceedings of the 12th Reconfigurable Architectures Workshop, Denver, CO, April 2005.