Multiple data set reduction on FPGAs

Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

Volumn , Issue , 2010, Pages 45-52

  Tai, Yi Gang ^a   Dan Lo, Chia Tien ^b   Psarris, Kleanthis ^a  

^a University of Texas at San Antonio   (United States)

^b SOUTHERN POLYTECHNIC STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER SIZES; DATA HAZARDS; ENGINEERING APPLICATIONS; EXECUTION TIME; INPUT DATAS; LOW LATENCY; MULTIPLE DATA; MULTIPLE SET; Q R DECOMPOSITION; RESOURCE USAGE; SEQUENTIAL DATA;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

DATA REDUCTION;

EID: 79551570275     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2010.5681654     Document Type: Conference Paper

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