An improved reduction algorithm with deeply pipelined operators

Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics

Volumn , Issue , 2009, Pages 3060-3065

  Tai, Yi Gang ^a   Lo, Chia Tien Dan ^a   Psarris, Kleanthis ^a  

^a University of Texas at San Antonio   (United States)

Author keywords

Algorithm; Architecture; Pipeline; Reduction

Indexed keywords

ALGORITHM ARCHITECTURES; DATA HAZARDS; DATA SETS; INNER PRODUCT; INPUT DATAS; LIN'S METHOD; MATRIX VECTOR MULTIPLICATION; MODIFIED DESIGNS; PROPER DESIGN; REDUCTION ALGORITHMS; REDUCTION OPERATION; SCIENTIFIC APPLICATIONS; SEQUENTIAL DATA;

CYBERNETICS; MATHEMATICAL OPERATORS; PIPELINES;

DATA REDUCTION;

EID: 74849104613     PISSN: 1062922X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSMC.2009.5345939     Document Type: Conference Paper

References (8)

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8. L. Zhuo, G. R. Morris, and V. K. Prasanna, "High-performance reduction circuits using deeply pipelined operators on FPGAs," IEEE Trans. Parallel Distrib. Syst., vol. 18, no. 10, pp. 1377-1392, October 2007.