A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 1, 2012, Pages 23-34

  Jeon, Dongsuk ^a   Seok, Mingoo ^b   Chakrabarti, Chaitali ^a   Blaauw, David ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Fast Fourier Transform (FFT); subthreshold CMOS circuits; super pipelining; ultra low voltage (ULV) design

Indexed keywords

ACTIVE CURRENT; AVERAGING EFFECT; CLOCK FREQUENCY; DESIGN APPROACHES; ENERGY EFFICIENT; ENERGY RATIO; FIRST-IN-FIRST-OUT; FUNCTIONAL UNITS; IMPROVING PERFORMANCE; LEAKAGE ENERGIES; LOGIC DEPTH; LOW POWER; LOW SUPPLY VOLTAGES; MEMORY SIZE; PERFORMANCE IMPROVEMENTS; SUBTHRESHOLD; SUBTHRESHOLD CMOS CIRCUITS; SUPER-PIPELINING; ULTRA-LOW-VOLTAGE; VARIATION TOLERANCES;

CLOCK DISTRIBUTION NETWORKS; CMOS INTEGRATED CIRCUITS; DESIGN; FAST FOURIER TRANSFORMS; MEMORY ARCHITECTURE; PIPE; PLATINUM COMPOUNDS;

ENERGY EFFICIENCY;

EID: 84655166985     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2169311     Document Type: Article

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