A Low-Power, High-Performance, 1024-Point FFT Processor

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 3, 1999, Pages 380-387

  Baas, Bevan M ^a,b,c,d  

^a STANFORD UNIVERSITY   (United States)

^b CALIFORNIA POLYTECHNIC STATE UNIVERSITY   (United States)

^c STANFORD UNIVERSITY   (United States)

^d HEWLETT PACKARD COMPANY   (United States)

Author keywords

Cache memories; Chip; CMOS digital integrated circuits; CMOS integrated circuits; digital signal processors (DSP's); discrete Fourier transforms (DFT's); energy efficient; FFT; Fourier transforms; low power; memory architecture

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FAST FOURIER TRANSFORMS;

FAST FOURIER TRANSFORM (FFT) PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0033098378     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.748190     Document Type: Article

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