Clock network design for ultra-low power applications

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2010, Pages 271-276

  Seok, Mingoo ^a   Blaauw, David ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Clock network; Robust design; Ultra low power

Indexed keywords

CLOCK NETWORK; CLOCK SIGNAL; DESIGN METHODOLOGY; ENERGY CONSUMPTION; ENVIRONMENTAL VARIATIONS; HOLD TIME; ROBUST DESIGNS; SUPPLY VOLTAGES; TECHNOLOGY SCALING; ULTRA-LOW POWER; ULTRALOW POWER APPLICATION; ULTRALOW VOLTAGE;

DESIGN; ENERGY UTILIZATION; POWER ELECTRONICS; SENSITIVITY ANALYSIS;

ELECTRIC CLOCKS;

EID: 77957943636     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1840845.1840901     Document Type: Conference Paper

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