Orion 2.0: A power-area simulator for interconnection networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 1, 2012, Pages 191-196

  Kahng, Andrew B ^a   Li, Bin ^b   Peh, Li Shiuan ^c   Samadi, Kambiz ^d  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

^c Department of Electrical Engineering and Computer Science   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Architectural level modeling; Design space exploration; Network on chip (NoC)

Indexed keywords

ACCURACY IMPROVEMENT; DESIGN CONSTRAINTS; DESIGN SPACE EXPLORATION; FIRST-ORDER; MULTICORE CHIPS; NETWORK ON CHIP; NETWORKS ON CHIPS;

VLSI CIRCUITS;

SPACE RESEARCH;

EID: 83655192624     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2091686     Document Type: Conference Paper

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