|
Volumn 44, Issue 1, 2011, Pages 339-344
|
An optimized design of 10-nm-scale dual-material surrounded gate MOSFETs for digital circuit applications
|
Author keywords
[No Author keywords available]
|
Indexed keywords
ANALYTICAL EXPRESSIONS;
CIRCUIT APPLICATION;
DRAIN-INDUCED BARRIER LOWERING;
ELECTRICAL PARAMETER;
ELECTRICAL PERFORMANCE;
GATE STRUCTURE;
GEOMETRICAL PARAMETERS;
MEMORY APPLICATIONS;
MOSFETS;
MULTI OBJECTIVE;
NANO SCALE;
OBJECTIVE FUNCTIONS;
OPTIMIZED DESIGNS;
SHORT-CHANNEL EFFECT;
SUBTHRESHOLD;
SUBTHRESHOLD SWING;
ELECTRIC NETWORK ANALYSIS;
ELECTRIC PROPERTIES;
MATHEMATICAL MODELS;
MULTIOBJECTIVE OPTIMIZATION;
NANOSTRUCTURED MATERIALS;
NANOTECHNOLOGY;
MOSFET DEVICES;
|
EID: 80054688717
PISSN: 13869477
EISSN: None
Source Type: Journal
DOI: 10.1016/j.physe.2011.09.007 Document Type: Article |
Times cited : (43)
|
References (22)
|