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Volumn 44, Issue 1, 2011, Pages 339-344

An optimized design of 10-nm-scale dual-material surrounded gate MOSFETs for digital circuit applications

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL EXPRESSIONS; CIRCUIT APPLICATION; DRAIN-INDUCED BARRIER LOWERING; ELECTRICAL PARAMETER; ELECTRICAL PERFORMANCE; GATE STRUCTURE; GEOMETRICAL PARAMETERS; MEMORY APPLICATIONS; MOSFETS; MULTI OBJECTIVE; NANO SCALE; OBJECTIVE FUNCTIONS; OPTIMIZED DESIGNS; SHORT-CHANNEL EFFECT; SUBTHRESHOLD; SUBTHRESHOLD SWING;

EID: 80054688717     PISSN: 13869477     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.physe.2011.09.007     Document Type: Article
Times cited : (43)

References (22)
  • 13
    • 80054707862 scopus 로고    scopus 로고
    • ATLAS: 2D Device Simulator, SILVACO International 2008
    • ATLAS: 2D Device Simulator, SILVACO International 2008.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.