TCAD study on gate-all-around cylindrical (GAAC) transistor for CMOS scaling to the end of the roadmap

Microelectronics Journal

Volumn 40, Issue 12, 2009, Pages 1766-1771

  Xiao, Deyuan ^a   Wang, Xi ^a   Yu, Yuehui ^a   Chen, Jing ^a   Zhang, Miao ^a   Xue, Zhongying ^a   Luo, Jiexin ^a  

^a SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY   (China)

Author keywords

Device physics; Fabrication procedure; Gate all around cylindrical (GAAC) transistor; TCAD simulation

Indexed keywords

DEVICE PHYSICS; FABRICATION PROCEDURE; GATE-ALL-AROUND; GATE-ALL-AROUND CYLINDRICAL (GAAC) TRANSISTOR; TCAD SIMULATION;

FABRICATION; TECHNOLOGICAL FORECASTING;

FIELD EFFECT TRANSISTORS;

EID: 70449674206     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2009.09.008     Document Type: Article

References (11)

1. B. Yu, L.L. Chang, S. Ahmed, et al., FinFET scaling to 10 nm gate length, in: International Electron Devices Meeting Technical Digest, 2002, p. 251.
2. B. Doyle, B. Boyanov, S. Datta, et al., Tri-gate fully-depleted CMOS transistors: fabrication, design and layout, Symposium on VLSI Technology Technical Digest Paper, 2003, p. 10A-2.
3. F.L. Yang, D. Lee, H.Y. Chen, et al., 5 nm-gate nanowire FinFET, Symposium on VLSI Technology Technical Digest Paper, 2004, p. 196.
4. Jiménez D., Iñíguez B., Suñé J., et al. Continuous analytic I-V model for surrounding-gate MOSFETs. IEEE Electron Device Letters 25 8 (2004) 571-573
5. Park J.T., and Colinge J.P. Multiple-gate SOI MOSFETs: device design guidelines. IEEE Transactions on Electron Device 49 12 (2002) 2222
6. J.P. Colinge, J.T. Park, C.A. Colinge, SOI devices for sub-0.1 μm gate lengths, in: Proceedings of the 23rd International Conference on Microelectronics, 2002, p. 109.
7. Colinge J.P., Park J.W., and Xiong W. Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs. IEEE Electron Device Letters 24 8 (2003) 515
8. Pei G., Ni W.P., Abhishek V.K., et al. A physical compact model of DG MOSFET for mixed-signal circuit applications-part I: model description. IEEE Transactions on Electron Devices 50 10 (2003) 2135
9. Kedzierski J., et al. Novel method for silicon quantum wire transistor fabrication. Journal of Vacuum Science and Technology B 17 6 (1999) 3244-3247
10. N. Singh, et al., Ultra-narrow silicon nanowire gate-all-around CMOS devices: impact of diameter, channel-orientation and low temperature on device performance, in: Proceedings of IEDM-2006 conference, pp. 547-550.
11. Singh N., et al. High-performance fully depleted silicon nanowire (diameter<5 nm) gate-all-around CMOS devices. IEEE Electron Device Letters 28 7 (2007) 547-550