Analytical model of subthreshold current and slope for asymmetric 4-T and 3-T double-gate MOSFETs

IEEE Transactions on Electron Devices

Volumn 55, Issue 12, 2008, Pages 3442-3449

  Dey, Aritra ^a,b   Chakravorty, Anjan ^a   DasGupta, Nandita ^a   DasGupta, Amitava ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

^b ARIZONA STATE UNIVERSITY   (United States)

Author keywords

Analytical model; Double gate (DG); Drain induced barrier lowering (DIBL); Silicon on insulator (SOI); Subthreshold current; Subthreshold slope

Indexed keywords

DRAIN CURRENT; GALERKIN METHODS; MODELS; PORT TERMINALS; SEMICONDUCTING SILICON COMPOUNDS; SILICON;

ANALYTICAL MODEL; DOUBLE GATE (DG); DRAIN-INDUCED BARRIER LOWERING (DIBL); SILICON-ON-INSULATOR (SOI); SUBTHRESHOLD CURRENT; SUBTHRESHOLD SLOPE;

MOSFET DEVICES;

EID: 57149127392     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2006109     Document Type: Article

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