Junctionless Nanowire Transistor (JNT): Properties and design guidelines

Solid-State Electronics

Volumn 65-66, Issue 1, 2011, Pages 33-37

  Colinge, J P ^a   Kranti, A ^a   Yan, R ^a   Lee, C W ^a   Ferain, I ^a   Yu, R ^a   Akhavan, N D ^a   Razavi, P ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

Fin FET; MOSFET; Multigate FET; Nanowire transistor

Indexed keywords

ACCUMULATION MODES; BULK CONDUCTION; BULK SILICON; CONDUCTION MECHANISM; CURRENT DRIVES; DESIGN GUIDELINES; DOPING CONCENTRATION; ELECTRICAL CHARACTERISTIC; FIN FET; FULLY DEPLETED; GATE CAPACITANCE; GATE ELECTRODES; HEAVILY DOPED; INTRINSIC DEVICE; MOSFET; MULTIGATE FET; NANOWIRE TRANSISTOR; NANOWIRE TRANSISTORS; PHYSICAL PARAMETERS; SILICON CHANNEL; SURFACE CHANNEL; VARIABLE RESISTORS;

MESFET DEVICES; MOS DEVICES; NANOWIRES; RESISTORS; TRANSISTORS;

ELECTRIC WIRE;

EID: 80054023209     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2011.06.004     Document Type: Conference Paper

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