-
1
-
-
0036508201
-
CMOS design near the limit of scaling
-
Taur, Y. CMOS design near the limit of scaling IBM J. Res. Dev. 2002, 46, 213
-
(2002)
IBM J. Res. Dev.
, vol.46
, pp. 213
-
-
Taur, Y.1
-
2
-
-
0036507826
-
Maintaining the benefits of CMOS scaling when scaling bogs down
-
Nowak, E. J. Maintaining the benefits of CMOS scaling when scaling bogs down IBM J. Res. Dev. 2002, 46, 169
-
(2002)
IBM J. Res. Dev.
, vol.46
, pp. 169
-
-
Nowak, E.J.1
-
3
-
-
77649185643
-
Th engineering
-
Th engineering IEEE Trans. Electron Devices 2010, 57, 626
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, pp. 626
-
-
Hussain, M.M.1
Smith, C.E.2
Harris, R.3
Young, C.4
Sassman, B.5
Tseng, H.-H.6
Jammy, R.7
-
4
-
-
35748932911
-
Nanoelectronics from the bottom up
-
Lu, W.; Lieber, C. M. Nanoelectronics from the bottom up Nat. Mater. 2007, 6, 841
-
(2007)
Nat. Mater.
, vol.6
, pp. 841
-
-
Lu, W.1
Lieber, C.M.2
-
5
-
-
0023421993
-
Double-Gate Silicon-on-Insulator Transistor with Volume Inversion: A New Device with Greatly Enhanced Performance
-
Balestra, F.; Cristoloveanu, S.; Benachir, M.; Brini, J.; Elewa, T. Double-Gate Silicon-on-Insulator Transistor with Volume Inversion: A New Device with Greatly Enhanced Performance IEEE Electron Device Lett. 1987, 8, 410
-
(1987)
IEEE Electron Device Lett.
, vol.8
, pp. 410
-
-
Balestra, F.1
Cristoloveanu, S.2
Benachir, M.3
Brini, J.4
Elewa, T.5
-
6
-
-
0035872875
-
Monte Carlo simulation of double-gate silicon-on-insulator inversion layers: The role of volume inversion
-
DOI 10.1063/1.1358321
-
Gamiz, F.; Fischetti, M. V. Monte Carlo simulation of double-gate silicon-on-insulator inversion layers: The role of volume inversion J. Appl. Phys. 2001, 89, 5478 (Pubitemid 32492130)
-
(2001)
Journal of Applied Physics
, vol.89
, Issue.10
, pp. 5478
-
-
Gamiz, F.1
Fischetti, M.V.2
-
7
-
-
79951480054
-
Programmable nanowire circuits for nanoprocessors
-
Yan, H.; Choe, H S.; Nam, S.; Hu, Y.; Das, S.; Klemic, J. F.; Ellenbogen, J. C.; Lieber, C. M. Programmable nanowire circuits for nanoprocessors Nature 2011, 470, 240
-
(2011)
Nature
, vol.470
, pp. 240
-
-
Yan, H.1
Choe, H.S.2
Nam, S.3
Hu, Y.4
Das, S.5
Klemic, J.F.6
Ellenbogen, J.C.7
Lieber, C.M.8
-
8
-
-
77957884572
-
Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
-
Bangsaruntip, S.; Majumdar, A.; Cohen, G. M.; Engelmann, S. U.; Zhang, Y.; Guillorn, M.; Gignac, L. M.; Mittal, S.; Graham, W. S.; Joseph, E. A.; Klaus, D. P.; Chang, J.; Cartier, E. A.; Sleight, J. W. Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm Symp. VLSI Technol., Dig. Tech. Pap. 2010, 21
-
(2010)
Symp. VLSI Technol., Dig. Tech. Pap.
, pp. 21
-
-
Bangsaruntip, S.1
Majumdar, A.2
Cohen, G.M.3
Engelmann, S.U.4
Zhang, Y.5
Guillorn, M.6
Gignac, L.M.7
Mittal, S.8
Graham, W.S.9
Joseph, E.A.10
Klaus, D.P.11
Chang, J.12
Cartier, E.A.13
Sleight, J.W.14
-
9
-
-
0037074809
-
Low-temperature selective epitaxy of silicon with chlorinated chemistry by RTCVD
-
Ribot, P.; Dutartre, D. Low-temperature selective epitaxy of silicon with chlorinated chemistry by RTCVD Mater. Sci. Eng., B. 2002, 89, 306
-
(2002)
Mater. Sci. Eng., B.
, vol.89
, pp. 306
-
-
Ribot, P.1
Dutartre, D.2
-
10
-
-
33745327664
-
Ge/Si nanowire heterostructures as high-performance field-effect transistors
-
Xiang, J.; Lu, W.; Hu, Y.; Wu, Y.; Yan, H.; Lieber, C. M. Ge/Si nanowire heterostructures as high-performance field-effect transistors Nature 2006, 441, 489
-
(2006)
Nature
, vol.441
, pp. 489
-
-
Xiang, J.1
Lu, W.2
Hu, Y.3
Wu, Y.4
Yan, H.5
Lieber, C.M.6
-
11
-
-
50549104030
-
Epitaxial growth of silicon nanowires using an aluminium catalyst
-
Wang, Y.; Schmidt, V.; Senz, S.; Gösele, U. Epitaxial growth of silicon nanowires using an aluminium catalyst Nat. Nanotechnol. 2006, 1, 186
-
(2006)
Nat. Nanotechnol.
, vol.1
, pp. 186
-
-
Wang, Y.1
Schmidt, V.2
Senz, S.3
Gösele, U.4
-
12
-
-
46049119669
-
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
-
Singh, N.; Lim, F. Y.; Fang, W. W.; Rustagi, S. C.; Bera, L. K.; Agarwal, A.; Tung, C. H.; Hoe, K. M.; Omampuliyur, S. R.; Tripathi, D.; Adeyeye, A. O.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. L. Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance IEEE Int. Electron Devices Meet., Tech. Dig. 2006, 1
-
(2006)
IEEE Int. Electron Devices Meet., Tech. Dig.
, pp. 1
-
-
Singh, N.1
Lim, F.Y.2
Fang, W.W.3
Rustagi, S.C.4
Bera, L.K.5
Agarwal, A.6
Tung, C.H.7
Hoe, K.M.8
Omampuliyur, S.R.9
Tripathi, D.10
Adeyeye, A.O.11
Lo, G.Q.12
Balasubramanian, N.13
Kwong, D.L.14
-
13
-
-
77952331615
-
High Performance 32nm Logic Technology Featuring 2nd Generation High-K + Metal Gate Transistors
-
Packan, P.; Akbar, S.; Armstrong, M.; Bergstrom, D.; Brazier, M.; Deshpande, H.; Dev, K.; Ding, G.; Ghani, T.; Golonzka, O.; Han, W.; He, J.; Heussner, R.; James, R.; Jopling, J.; Kenyon, C.; Lee, S.-H.; Liu, M.; Lodha, S.; Mattis, B.; Murthy, A.; Neiberg, L.; Neirynck, J.; Pae, S.; Parker, C.; Pipes, L.; Sebastian, J.; Seiple, J.; Sell, B.; Sharma, A.; Sivakumar, S.; Song, B.; St. Amour, A.; Tone, K.; Troeger, T.; Weber, C.; Zhang, K.; Luo, Y.; Natarajan, S. High Performance 32nm Logic Technology Featuring 2nd Generation High-K + Metal Gate Transistors IEEE Int. Electron Devices Meet., Tech. Dig. 2009, 28.4.1
-
(2009)
IEEE Int. Electron Devices Meet., Tech. Dig.
, pp. 2841
-
-
Packan, P.1
Akbar, S.2
Armstrong, M.3
Bergstrom, D.4
Brazier, M.5
Deshpande, H.6
Dev, K.7
Ding, G.8
Ghani, T.9
Golonzka, O.10
Han, W.11
He, J.12
Heussner, R.13
James, R.14
Jopling, J.15
Kenyon, C.16
Lee, S.-H.17
Liu, M.18
Lodha, S.19
Mattis, B.20
Murthy, A.21
Neiberg, L.22
Neirynck, J.23
Pae, S.24
Parker, C.25
Pipes, L.26
Sebastian, J.27
Seiple, J.28
Sell, B.29
Sharma, A.30
Sivakumar, S.31
Song, B.32
St. Amour, A.33
Tone, K.34
Troeger, T.35
Weber, C.36
Zhang, K.37
Luo, Y.38
Natarajan, S.39
more..
-
14
-
-
41149171855
-
Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering
-
Kavalieros, J.; Doyle, B.; Datta, S.; Dewey, G.; Doczy, M.; Jin, B.; Lionberger, D.; Metz, M.; Rachmady, W.; Radosavljevic, M.; Shah, U.; Zelick, N.; Chau, R. Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering Symp. VLSI Technol., Dig. Tech. Pap. 2006, 50
-
(2006)
Symp. VLSI Technol., Dig. Tech. Pap.
, pp. 50
-
-
Kavalieros, J.1
Doyle, B.2
Datta, S.3
Dewey, G.4
Doczy, M.5
Jin, B.6
Lionberger, D.7
Metz, M.8
Rachmady, W.9
Radosavljevic, M.10
Shah, U.11
Zelick, N.12
Chau, R.13
-
15
-
-
79951849369
-
Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape
-
Hashemi, P.; Teherani, J.; Hoyt, J. Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape. IEEE Int. Electron Devices Meet., Tech. Dig. 2010, 34, 5.1.
-
(2010)
IEEE Int. Electron Devices Meet., Tech. Dig.
, vol.34
, pp. 51
-
-
Hashemi, P.1
Teherani, J.2
Hoyt, J.3
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