MECCA: A robust low-overhead PUF using embedded memory array

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6917 LNCS, Issue , 2011, Pages 407-420

  Krishna, Aswin Raghav ^a   Narasimhan, Seetharam ^a   Wang, Xinmu ^a   Bhunia, Swarup ^a  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

IC authentication; Memory failures; Negative Bias Temperature Instability (NBTI); Physical Unclonable Function (PUF)

Indexed keywords

CHALLENGE-RESPONSE PAIR; DUTY CYCLES; EMBEDDED MEMORIES; EMBEDDED MEMORY ARRAYS; EMBEDDED SECURITY; IC AUTHENTICATION; INTRINSIC PROCESS; MEMORY FAILURES; NEGATIVE BIAS TEMPERATURE INSTABILITY; ORIGINAL DESIGN; PHYSICAL UNCLONABLE FUNCTIONS; PROCESS VARIATION; REPRODUCIBILITIES; STATIC MEMORY; TAMPER-RESISTANT;

AUTHENTICATION; CELLS; CRYPTOGRAPHY; DESIGN; HAMMING DISTANCE; INTEGRATED CIRCUITS; INTELLECTUAL PROPERTY; RANDOM PROCESSES;

EMBEDDED SYSTEMS;

EID: 80053482200     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-23951-9_27     Document Type: Conference Paper

References (29)

1. ORS-LABS: Counterfeit Electronic Components - An Overview (2007), http://www.ors-labs.com/pdf/MASH07CounterfeitDevice.pdf
2. Kocher, P., Jaffe, J., Jun, B.: Differential power analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388-397. Springer, Heidelberg (1999)
3. Kulikowski, K.J., Karpovsky, M.G., Taubin, A.: DPA on faulty cryptographic hardware and countermeasures. In: Breveglieri, L., Koren, I., Naccache, D., Seifert, J.-P. (eds.) FDTC 2006. LNCS, vol. 4236, pp. 211-222. Springer, Heidelberg (2006) (Pubitemid 44850482)
4. Gassend, B., et al.: Controlled Physical Random Functions. In: Proceedings of 18th Annual Computer Security Applications Conference (2002)
5. Gassend, B., et al.: Silicon Physical Random Functions. In: Proceedings of the Computer and Communication Security Conference (2002)
6. Suh, G.E., Devadas, S.: Physical Unclonable Functions for Device Authentication and Secret Key Generation. In: Proc. DAC, pp. 9-14 (2007)
7. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS) (2005)
8. Ney, A., et al.: A New Design-For-Test Technique for SRAM Core-Cell Stability Faults. In: Proc. DATE, pp. 1344-1348 (2009)
9. Wang, X., Tehranipoor, M.: Novel Physical Unclonable Function with Process and Environmental Variations. In: Proc. DATE, pp. 1065-1070 (2010)
10. Maiti, A., Schaumont, P.: Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive. Journal of Cryptology, 1-23 (2010)
11. Pappu, R.: Physical One-Way Functions, Phd thesis, Massachusetts Institute of Technology (2001)
12. Ozturk, E., Hammouri, G., Sunar, B.: Physical Unclonable Function with Tristate Buffers. In: Proc. ISCAS, pp. 3194-3197 (2008)
13. Guajardo, J., Kumar, S.S., Schrijen, G.J., Tuyls, P.: FPGA Intrinsic PUFs and Their Use for IP Protection. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 63-80. Springer, Heidelberg (2007)
14. Holcomb, D., Burleson, W., Fu, K.: Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags. In: Proc. the Conference on RFID Security (2007)
15. Su, Y., Holleman, J., Otis, B.: A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations. In: Proc. ISSCC, pp. 15-17 (2007)
16. Kumar, S., Guajardo, J., Maes, R., Schrijen, G., Tuyls, P.: The Butterfly PUF: Protecting IP on Every FPGA. In: Proc. HOST (2008)
17. Guajardo, J., Kumar, S., Tuyls, P., Schrijen, G. : Identification Of Devices Using Physically Unclonable Functions. WIPO Patent Application WO/2009/024913 A2
18. Guyensu, T.: Using Data Contention in Dual-ported Memories for Security Applications. Journal of Signal Processing Systems (2010)
19. Gassend, B., Clarke, D., van Dijkm, M., Devadas, S.: Controlled Physical Random Functions. In: Proc. ACSAC (2002)
20. Mukhopadhyay, S., Mahmoodi, H., Roy, K.: Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS. In: IEEE TCAD, pp. 1859-1880 (2005)
21. Mukhopadhyay, S., Mahmoodi, H., Roy, K.: Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. In: IEEE TCAD, pp. 174-183 (2008)
22. Luo, H., Wang, Y., He, K., Luo, R., Yang, H., Xie, Y.: Modeling of PMOS NBTI Effect Considering Temperature Variation. In: Proc. ISQED, pp. 139-144 (2007)
23. Kumar, S.V., Kim, K.H., Sapatnekar, S.S.: Impact of NBTI on SRAM Read Stability and Design for Reliability. In: Proc. ISQED (2006)
24. Paul, B.C., Kang, K., Kufluoglu, H., Alam, M.A., Roy, K.: Impact of NBTI on the Temporal Performance Degradation of Digital Circuits. IEEE Electron Devices, 560-562 (2005)
25. Kang, K., Gangwal, S., Park, S.P., Roy, K.: NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can we Approach a Reliability Solution? In: Proc. ASP-DAC (2008)
26. Bansal, A., et al.: Impacts of NBTI and PBTI on SRAM Static/Dynamic Noise Margins and Cell Failure Probability. In: Microelectronics Reliability, pp. 642-649 (2009)
27. Yang, S., Yang, H., Chuang, C., Hwang, W.: Timing Control Degradation and NBTI/PBTI Tolerant Design for Write-Replica Circuit in Nanoscale CMOS SRAM. In: Proc. VLSI-DAT, pp. 162-165 (2009)
28. Predictive Technology Model, http://www.eas.asu.edu/~ptm/
29. Maiti, A., Casarona, J., McHale, L., Schaumont, P.: A Large Scale Characterization of RO-PUF. In: Proc. HOST, pp. 94-99 (2010)