Timing control degradation and NBTI/PBTI tolerant design for Write-replica circuit in nanoscale CMOS SRAM

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Volumn , Issue , 2009, Pages 162-165

  Yang, Shyh Chyi ^a   Yang, Hao I ^a   Chuang, Ching Te ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS TEMPERATURE INSTABILITY; CMOS TECHNOLOGY; METAL-GATE; NANO SCALE; NANOSCALE CMOS; NEGATIVE BIAS TEMPERATURE INSTABILITY; PERFORMANCE DEGRADATION; POLY GATES; STRESS TIME; SUPPLY LINES; TIMING CONTROL; TIMING-CRITICAL CIRCUITS; WRITE MARGIN; WRITE OPERATIONS;

CMOS INTEGRATED CIRCUITS; COMPUTER CRIME; DEGRADATION; DESIGN; GATES (TRANSISTOR); METAL RECOVERY; NANOSTRUCTURED MATERIALS; NEGATIVE TEMPERATURE COEFFICIENT; RAILROAD TUNNELS; STATIC RANDOM ACCESS STORAGE; THERMODYNAMIC STABILITY; TIME MEASUREMENT;

TIMING CIRCUITS;

EID: 77950688244     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2009.5158120     Document Type: Conference Paper

References (5)

1. R. Vattikonda et al., "Modeling and minimization of PMOS NBTI effect for robust nanometer design," DAC, pp. 1047-1052, 2006. (Pubitemid 47114050)
2. K. Kang et al., "Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis," IEEE T-CAD, pp. 1770-1781, Oct. 2007. (Pubitemid 47483019)
3. http://www.eas.asu.edu/~ptm/.
4. S. Zafar et al., "A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates," Symp. VLSI Tech., pp. 23-25, 2006. (Pubitemid 351424107)
5. T. Suzuki et al. "A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme," IEEE JSSC, pp. 152-160, Jan. 2006. (Pubitemid 43145973)