A new design-for-test technique for SRAM core-cell stability faults

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 1344-1348

  Ney, A ^a   Dilillo, L ^a   Girard, P ^a   Pravossoudovitch, S ^a   Virazel, A ^a   Bastian, M ^b   Gouin, V ^b  

^a UNIV MONTPELLIER   (France)

^b Infineon Technologies France   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; FAULT DETECTION; INTEGRATED CIRCUIT DESIGN; LOGIC DESIGN; SEMICONDUCTOR STORAGE; STABILITY; STATIC RANDOM ACCESS STORAGE;

DESIGN FOR TEST; PROGRAMMABILITY; SAFETY APPLICATIONS; SEMICONDUCTOR MEMORY; SRAM CORE-CELL; SRAM DESIGN; TEST APPLICATION TIME; VOLTAGE LEVELS;

CYTOLOGY;

EID: 70350048913     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090873     Document Type: Conference Paper

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