Operation of SiC normally-off JFET at the edges of its safe operating area

Microelectronics Reliability

Volumn 51, Issue 9-11, 2011, Pages 1767-1772

  Abbate, Carmine ^a   Busatto, Giovanni ^a   Iannuzzo, Francesco ^a  

^a UNIVERSITY OF CASSINO AND SOUTHERN LAZIO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DAMAGED AREA; DEVICE FAILURES; DEVICE UNDER TEST; EDGE TERMINATION; EXPERIMENTAL CHARACTERIZATION; EXPERIMENTAL SETUP; GATE METALLIZATION; NON DESTRUCTIVE; PROTECTION CIRCUITS; SAFE OPERATING AREA; SECOND BREAKDOWN; SHORT CIRCUIT; SURFACE METALLIZATION;

METALLIZING; SEMICONDUCTOR DEVICES; SILICON CARBIDE;

EQUIPMENT;

EID: 80052917220     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2011.07.055     Document Type: Conference Paper

References (10)

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