High speed redundant self-correcting circuits for radiation hardened by design logic

Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

Volumn , Issue , 2009, Pages 465-472

  Hindman, Nathan D ^a   Pettit, David E ^a   Patterson, Dan W ^a   Nielsen, Kyle E ^a   Yao, Xiaoyin ^b   Holbert, Keith E ^a   Clark, Lawrence T ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

^b NONE

Author keywords

microprocessor; Radiation hardening by design; redundant systems; registers

Indexed keywords

BULK CMOS; CACHE DESIGN; CLOCK FREQUENCY; CLOCK GATING; CURRENT INCREASE; DATA PATHS; FEEDBACK PATHS; LOW STAND-BY POWER; MAJORITY GATES; MICROPROCESSOR; RADIATION HARDENED BY DESIGN; RADIATION HARDENING BY DESIGN; REDUNDANT CIRCUITS; REDUNDANT SYSTEM; REGISTERS; SINGLE EVENT UPSETS; TRANSIENT RADIATION; TRIPLE MODULAR REDUNDANT;

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; DESIGN; HARDENING; RADIATION EFFECTS; STATE FEEDBACK; TRANSIENTS;

RADIATION HARDENING;

EID: 80052747346     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RADECS.2009.5994697     Document Type: Conference Paper

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