Reducing pin and area overhead in fault-tolerant FPGA-based designs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 108-117

  Lima, Fernanda ^a   Carro, Luigi ^a   Reis, Ricardo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Fault tolerance; FPGA

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SYSTEM RECOVERY; ELECTRIC POWER SUPPLIES TO APPARATUS; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; RELIABILITY; SEQUENTIAL CIRCUITS; STATIC RANDOM ACCESS STORAGE;

POWER DISSIPATION; TRANSIENT FAULTS; TRIPLE MODULAR REDUNDANCY;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0038005997     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611817.611834     Document Type: Conference Paper

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