Buffer-integrated-cache: A cost-effective SRAM architecture for handheld and embedded platforms

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 966-971

  Fajardo, Carlos Flores ^a   Fang, Zhen ^a   Iyer, Ravi ^a   Garcia, German Fabila ^a   Lee, Seung Eun ^b   Zhao, Li ^a  

^a INTEL CORPORATION   (United States)

^b Seoul National University of Science and Technology   (South Korea)

Author keywords

Accelerator; Cache; Memory; System on Chip

Indexed keywords

ACCELERATOR; CACHE; CACHE MISS; EMBEDDED PLATFORMS; HANDHELDS; L2 CACHE; MEMORY; PENTIUM; SYSTEM ON CHIPS;

ACCELERATION; APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUGMENTED REALITY; BUFFER STORAGE; COMPUTER AIDED DESIGN; COST EFFECTIVENESS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; SPEECH RECOGNITION; VIRTUAL REALITY;

STATIC RANDOM ACCESS STORAGE;

EID: 80052679438     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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