Multi-level memory system architecture for high performance DSP applications

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2000, Pages 408-413

  Agarwala, Sanjive ^a   Fuoco, Charles ^a   Anderson, Tim ^a   Comisky, Dave ^a   Mobley, Christopher ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; PROGRAM PROCESSORS;

CENTRAL PROCESSING UNITS (CPU); MULTI-LEVEL MEMORY SYSTEM ARCHITECTURES;

RANDOM ACCESS STORAGE;

EID: 0033711557     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)