Performance measurement of an integrated NIC architecture with 10GbE

Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects

Volumn , Issue , 2009, Pages 52-59

  Liao, Guangdeng ^a   Bhuyan, Laxmi ^a  

^a University of California Riverside ^*  (United States)

Author keywords

10GbE; Characterization; Discrete NIC; Integrated NIC; Performace evaluation; Sun Niagara 2

Indexed keywords

10-GIGABIT ETHERNET (10-GBE); 100 GBE; 10GBE; CACHE MISS; CPU UTILIZATION; NETWORK BANDWIDTH; NETWORK INTERFACE; PERFORMANCE BENEFITS; PERFORMANCE MEASUREMENTS; SIMULATION METHODOLOGY; SYSTEM BEHAVIORS; SYSTEM ON A CHIP;

ETHERNET; INTEGRATION; NANOTECHNOLOGY; PROGRAM PROCESSORS; SUN; TELECOMMUNICATION NETWORKS;

INTERFACES (COMPUTER);

EID: 77950938651     PISSN: 15504794     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HOTI.2009.16     Document Type: Conference Paper

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