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Volumn , Issue , 2008, Pages 1196-1201

Instruction cache energy saving through compiler way-placement

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CACHE MEMORY; INDUSTRIAL ENGINEERING; PROGRAM COMPILERS; TESTING;

EID: 49749100728     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484841     Document Type: Conference Paper
Times cited : (9)

References (16)
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    • Bellas, N.1
  • 2
    • 4544372203 scopus 로고    scopus 로고
    • XTREM: A power simulator for the Intel XScale core
    • G. Contreras et al. XTREM: a power simulator for the Intel XScale core. In LCTES, 2004.
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    • Contreras, G.1
  • 3
    • 0036294454 scopus 로고    scopus 로고
    • Drowsy caches: Simple techniques for reducing leakage power
    • K. Flautner et al. Drowsy caches: Simple techniques for reducing leakage power. In ISCA-29, 2002.
    • (2002) ISCA-29
    • Flautner, K.1
  • 4
    • 49749092414 scopus 로고    scopus 로고
    • MiBench: A free, commercially representative embedded benchmark suite
    • M. R. Guthaus et al. MiBench: A free, commercially representative embedded benchmark suite. In WWC-4 (MICRO-34), 2001.
    • (2001) WWC-4 (MICRO-34)
    • Guthaus, M.R.1
  • 5
    • 56749086216 scopus 로고    scopus 로고
    • Towards efficient supercomputing: A quest for the right metric
    • C.-H. Hsu et al. Towards efficient supercomputing: A quest for the right metric. In HP-PAC, 2005.
    • (2005) HP-PAC
    • Hsu, C.-H.1
  • 6
    • 0033363078 scopus 로고    scopus 로고
    • Way-predicting set-associative cache for high performance and low energy consumption
    • K. Inoue et al. Way-predicting set-associative cache for high performance and low energy consumption. In ISLPED, 1999.
    • (1999) ISLPED
    • Inoue, K.1
  • 8
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    • A non-uniform cache architecture for low power system design
    • T. Ishihara et al. A non-uniform cache architecture for low power system design. In ISLPED, 2005.
    • (2005) ISLPED
    • Ishihara, T.1
  • 9
    • 0035953633 scopus 로고    scopus 로고
    • Instruction cache organisation for embedded low-power processors
    • C. Jung et al. Instruction cache organisation for embedded low-power processors. IEE Electronics Letters, 37(9), 2001.
    • (2001) IEE Electronics Letters , vol.37 , Issue.9
    • Jung, C.1
  • 10
    • 0034856732 scopus 로고    scopus 로고
    • Cache decay: Exploiting generational behavior to reduce cache leakage power
    • S. Kaxiras et al. Cache decay: Exploiting generational behavior to reduce cache leakage power. In ISCA-28, 2001.
    • (2001) ISCA-28
    • Kaxiras, S.1
  • 11
    • 0002776275 scopus 로고    scopus 로고
    • The filter cache: An energy efficient memory structure
    • J. Kin et al. The filter cache: An energy efficient memory structure. In MICRO-30, 1997.
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    • Kin, J.1
  • 12
    • 49749086612 scopus 로고    scopus 로고
    • Way memoization to reduce fetch energy in instruction caches
    • A. Ma et al. Way memoization to reduce fetch energy in instruction caches. In WCED (ISCA-28), 2001.
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  • 13
    • 0030285348 scopus 로고    scopus 로고
    • A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
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  • 14
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    • R. A. Ravindran et al. Compiler managed dynamic instruction placement in a low-power code cache. In CGO, 2005.
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  • 15
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    • DIABLO: A reliable, retargetable and extensible link-time rewriting framework
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  • 16
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.