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Volumn , Issue , 2011, Pages

SoftHV: A HW/SW co-designed processor with horizontal and vertical fusion

Author keywords

co designed virtual machine; micro op fusion

Indexed keywords

ARITHMETIC OPERATIONS; CODE SEQUENCES; KEY FEATURE; LOW-COMPLEXITY; MICRO-OP FUSION; OUT-OF-ORDER PROCESSORS; PARALLEL LOADS; PERFORMANCE IMPROVEMENTS; SINGLE CYCLE; VIRTUAL MACHINES;

EID: 80052554252     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2016604.2016606     Document Type: Conference Paper
Times cited : (12)

References (24)
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    • IEEE Intl. Symp. on Microarchitecture, 2004
    • Clark, N.1
  • 4
    • 84935064025 scopus 로고    scopus 로고
    • Using branch handling hardware to support profile-driven optimization
    • T. Conte et al. Using branch handling hardware to support profile-driven optimization. In IEEE Intl. Symp. on Microarchitecture, 1994.
    • IEEE Intl. Symp. on Microarchitecture, 1994
    • Conte, T.1
  • 6
    • 84943385246 scopus 로고    scopus 로고
    • The Transmeta Code Morphing Software: Using speculation, recovery, and adaptive retranslation to address real-life challenges
    • J. Dehnert et al. The Transmeta Code Morphing Software: using speculation, recovery, and adaptive retranslation to address real-life challenges. In IEEE Intl. Symp. on Code Generation and Optimization, 2003.
    • IEEE Intl. Symp. on Code Generation and Optimization, 2003
    • Dehnert, J.1
  • 9
    • 0003278283 scopus 로고    scopus 로고
    • The Microarchitecture of the Pentium 4 Processor
    • G. Hinton et al. The Microarchitecture of the Pentium 4 Processor. Intel Technology Journal, 2001.
    • (2001) Intel Technology Journal
    • Hinton, G.1
  • 16
    • 0035363244 scopus 로고    scopus 로고
    • rePLay: A Hardware Framework for Dynamic Optimization
    • S. Patel et al. rePLay: A Hardware Framework for Dynamic Optimization. IEEE Transactions on Computers, 2001.
    • (2001) IEEE Transactions on Computers
    • Patel, S.1
  • 22
    • 80052526124 scopus 로고    scopus 로고
    • CHIMAERA: A High-Performance architecture with a tightly-coupled reconfigurable functional unit
    • Z. Ye et al. CHIMAERA: A High-Performance architecture with a tightly-coupled reconfigurable functional unit. In IEEE Intl. Symp. on Computer Architecture, 2000.
    • IEEE Intl. Symp. on Computer Architecture, 2000
    • Ye, Z.1
  • 23
    • 4644280001 scopus 로고    scopus 로고
    • From sequences of dependent instructions to functions: An approach for improving performance without ILP or speculation
    • S. Yehia et al. From sequences of dependent instructions to functions: An approach for improving performance without ILP or speculation. In IEEE Intl. Symp. on Computer Architecture, 2004.
    • IEEE Intl. Symp. on Computer Architecture, 2004
    • Yehia, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.