0.6 μm BiCMOS processor with dynamic execution

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 38, Issue , 1995, Pages

  Colwell, Robert P ^a   Steck, Randy L ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; GATES (TRANSISTOR); INTERFACES (COMPUTER); LOGIC CIRCUITS;

DYNAMIC EXECUTION MICROENGINE; INTEL ARCHITECTURE; LEVEL SENSITIVE SCAN DESIGN IMPLEMENTATION;

MICROPROCESSOR CHIPS;

EID: 0029256210     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)