Ultralow-latency hardware-in-the-loop platform for rapid validation of power electronics designs

IEEE Transactions on Industrial Electronics

Volumn 58, Issue 10, 2011, Pages 4708-4716

  Majstorovic, Dusan ^a,b   Celanovic, Ivan ^c   Teslic, Nikola Dj ^a,b   Celanovic, Nikola ^a,d   Katic, Vladimir A ^a  

^a UNIVERSITY OF NOVI SAD   (Serbia)

^b RT RK Computer Based Systems LLC   (Serbia)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d Typhoon RTDS   (Switzerland)

Author keywords

Automatic design verification; electronic design automation for power electronics (PE); field programmable gate array (FPGA) based ultralow latency (ULL) processor; hardware in the loop (HIL); real time digital simulator for PE and motor drives

Indexed keywords

AUTOMATIC DESIGN; CONTROL HARDWARES; DIGITAL PROCESSORS; ELECTRONIC DESIGN AUTOMATION FOR POWER ELECTRONICS (PE); ELECTRONICS DESIGN; HARD-WARE-IN-THE-LOOP; HARDWARE IN THE LOOP (HIL); PERFORMANCE OPTIMIZATIONS; PROCESSOR CORES; REAL-TIME DIGITAL SIMULATOR; SIMULATION TIME; SOFTWARE IMPLEMENTATION; SYSTEM PROTECTION; UNIFIED APPROACH;

AUTOMATIC TESTING; COMPUTER AIDED DESIGN; ELECTRIC DRIVES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FIRMWARE; POWER ELECTRONICS; SOFTWARE TESTING; VERIFICATION;

SOFTWARE DESIGN;

EID: 80052344994     PISSN: 02780046     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIE.2011.2112318     Document Type: Article

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