A floating-point accumulator for FPGA-based high performance computing applications

Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Volumn , Issue , 2009, Pages 493-499

  Sun, Song ^a   Zambreno, Joseph ^a  

^a Iowa State University of Science and Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARBITRARY NUMBER; BUILDING BLOCKES; CLOCK FREQUENCY; CLOCK SPEED; FIXED SIZE; FPGA TECHNOLOGY; HIGH PERFORMANCE COMPUTING SYSTEMS; HIGH-PERFORMANCE COMPUTING APPLICATIONS; INPUT SET; PRIOR KNOWLEDGE; RESOURCE USAGE; SPARSE MATRIX COMPUTATIONS; SUMMANDS;

DIGITAL ARITHMETIC; MATRIX ALGEBRA;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77949367863     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2009.5377624     Document Type: Conference Paper

References (12)

1. L. M.Ni and K. Hwang, "Vector-reduction techniques for arithmetic pipelines," IEEE Transactions on Computers, vol. c-34, no. 5, pp. 404-411, 1985.
2. U. Kulisch, "The fifth floating-point operation for top-performance computers," Universitat Karlsruhe, Tech. Rep., 1997.
3. S. Williams, L. Oliker, R. Vuduc, J. Shalf, K. Yelick, and J. Demmel, "Optimization of sparse matrx-vector multiplication on emerging multicore platforms," in Proceedings of Supercomputing (SC), 2007.
4. S. McGettrick, D. Geraghty, and C. McElroy, "An FPGA architecture for the PageRank eigenvector problem," in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2008, pp. 523-526.
5. L. Zhuo and V. Prasanna, "High-performance and area-efficient reduction circuits on FPGAs," in Proceedings of the International Symposium on Computer Architecture on High Performance Computing (SBACPAD), 2005, pp. 52-59.
6. L. Zhuo, G. Morris, and V. Prasanna, "Designing scalable FPGA-based reduction circuits using pipelined floating-point cores," in Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS), 2005.
7. -, "High-performance reduction circuits using deeply pipelined operators on FPGAs," IEEE Trans. Parallel Distrib. Syst., vol. 18, no. 10, pp. 1377-1392, 2007.
8. K. D. Underwood, K. S. Hemmert, and C. Ulmer, "Architectures and APIs: assessing requirements for delivering fpga performance to applications," in Proceedings of Supercomputing (SC), 2006.
9. P. M. Kogge, The Architecture of Pipelined Computers. Hemisphere Publishing Corporation, 1981.
10. F. de Dinechin, B. Pasca, O. Cret, and R. Tudoran, "An FPGA-specific approach to floating-point accumulation and sum-of-products," in International Conference on Field-Programmable Technology (FPT), 2008, pp. 33-40.
11. C. He, G. Qin, M. Lu, and W. Zhao, "Group-alignment based accurate floating-point summation on FPGAs," in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2006, pp. 136-142.
12. Double Precision Floating Point Core, www.opencores.org, OpenCores, 2009.