FPGA implementation of a single-precision floating-point multiply-accumulator with single-cycle accumulation

Proceedings - IEEE Symposium on Field Programmable Custom Computing Machines, FCCM 2009

Volumn , Issue , 2009, Pages 267-270

  Paidimarri, Arun ^a   Cevrero, Alessandro ^b   Brisk, Philip ^b   Ienne, Paolo ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; FPGA IMPLEMENTATIONS; INTERNAL REPRESENTATION; NON-TRADITIONAL; SINGLE CYCLE;

COMPUTERS; DIGITAL ARITHMETIC;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 74349105308     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2009.50     Document Type: Conference Paper

References (4)

1. S. R. Vangal, Y. V. Hoskote, N. Y. Borkar, and A. Alvandpour, "A 6.2-GFlops floating-point multiply-accumulator with conditional normalization." IEEE Journal of Solid State Circuits, vol. 41, no. 10, Oct. 2006, 2314-2323.
2. Z. Luo, and M. Martonosi, "Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques." IEEE Trans. Computers, vol. 49, no. 3, March, 2000, 208-218.
3. F. de Dinechin, B. Pasca, O. Cret, and R. Tudoran, "An FPGA-specific approach to floating-point accumulation and sum-of-products." Int. Conf. Field-Programmable Technology, Dec. 2008, pp. 33-40.
4. M. Langhammer, "Floating point datapath synthesis for FPGAs," Int. Conf. Field Programmable Logic and Applications, Sept. 2008, pp. 355-360.