Floating-point accumulation circuit for matrix applications

Proceedings - 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2006

Volumn , Issue , 2006, Pages 303-304

  Bodnar, Michael R ^a   Humphrey, John R ^b   Curt, Petersen F ^b   Durbano, James P ^b   Prather, Dennis W ^a  

^a UNIVERSITY OF DELAWARE   (United States)

^b EM PHOTONICS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33751555869     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2006.41     Document Type: Conference Paper

References (4)

1. J. P. Durbano, F. E. Ortiz, J. R. Humphrey, P. F. Curt, and D. W. Prather, "FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method," FCCM2004 Proceedings.
2. M. Leeser and X. Wang, "Variable precision floating-point division and square root," HPEC2004 Proceedings.
3. L. Zhuo, G. R. Morris, and V. K. Prasanna, "Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores," Reconfigurable Architectures Workshop, 2005.
4. L. Zhuo and V. K. Prasanna, "High-Performance and Area-Efficient Reduction Circuits on FPGAs," ISCA HPC2005 Proceedings.