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Volumn , Issue , 2005, Pages 542-547

Fast decap allocation algorithm for robust on-chip power delivery

Author keywords

[No Author keywords available]

Indexed keywords

ADJOINT NETWORK METHODS; ALLOCATION ALGORITHM; COMPUTATION METHODS; LINE SEARCHES; ON-CHIP DECOUPLING CAPACITORS; POWER DELIVERY; POWER/GROUND NETWORK; VOLTAGE FLUCTUATIONS;

EID: 33750598564     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.57     Document Type: Conference Paper
Times cited : (13)

References (17)
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    • H. H. Chen and D. D. Ling, "Power supply noise analysis methodology for deep-submicron VLSI chip design," in Proc. Design Automation Conf. (DAC), 1997, pp. 638-643.
    • (1997) Proc. Design Automation Conf. (DAC) , pp. 638-643
    • Chen, H.H.1    Ling, D.D.2
  • 4
    • 0001391562 scopus 로고
    • Automated network design-The frequency-domain case
    • Aug
    • S. W. Director and R. A. Rohrer, "Automated network design-the frequency-domain case," IEEE Trans. on Circuit Theory, vol. 16, no. 3, pp. 330-337, Aug. 1969.
    • (1969) IEEE Trans. on Circuit Theory , vol.16 , Issue.3 , pp. 330-337
    • Director, S.W.1    Rohrer, R.A.2
  • 5
    • 0000208736 scopus 로고
    • The generalized adjoint network and network sensitivities
    • Aug
    • -, "The generalized adjoint network and network sensitivities," IEEE Trans. on Circuit Theory, vol. 16, no. 3, pp. 318-323, Aug. 1969.
    • (1969) IEEE Trans. on Circuit Theory , vol.16 , Issue.3 , pp. 318-323
    • Director, S.W.1    Rohrer, R.A.2
  • 9
    • 33847368711 scopus 로고    scopus 로고
    • Simultaneous area minimization and decaps insertion for power delivery network using adjoint senstivity analysis with ieks method
    • Y.-M. Lee, J.-L. Tsai, and C. C.-P. Chen, "Simultaneous area minimization and decaps insertion for power delivery network using adjoint senstivity analysis with ieks method," in Proc. of VLSI Design/CAD Symposium, 2003.
    • (2003) Proc. of VLSI Design/CAD Symposium
    • Lee, Y.-M.1    Tsai, J.-L.2    Chen, C.C.-P.3
  • 10
    • 0034463485 scopus 로고    scopus 로고
    • On-chip decoupling capacitor optimization using architectural level current signature prediction
    • M. Pant, P. Pant, and D. Wills, "On-chip decoupling capacitor optimization using architectural level current signature prediction," in Proc. IEEE Midwest Symp. Circuits and Systems, 2000, pp. 772-775.
    • (2000) Proc. IEEE Midwest Symp. Circuits and Systems , pp. 772-775
    • Pant, M.1    Pant, P.2    Wills, D.3
  • 11
    • 0026866104 scopus 로고
    • Effectiveness of multiple decoupling capacitors
    • May
    • C. Paul, "Effectiveness of multiple decoupling capacitors," IEEE Trans. on Electromagnetic Compatibility, vol. 34, no. 2, pp. 130-133, May 1992.
    • (1992) IEEE Trans. on Electromagnetic Compatibility , vol.34 , Issue.2 , pp. 130-133
    • Paul, C.1
  • 13
    • 0036179950 scopus 로고    scopus 로고
    • Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
    • Jan
    • C. K. S. Zhao, K. Roy, "Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 81-92, Jan. 2002.
    • (2002) IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems , vol.21 , Issue.1 , pp. 81-92
    • Zhao, C.K.S.1    Roy, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.