Modeling program resource demand using inherent program characteristics

Performance Evaluation Review

Volumn 39, Issue 1 SPEC. ISSUE, 2011, Pages 1-12

  Chen, Jian ^a   John, Lizy K ^a   Kaseridis, Dimitris ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Microprocessor; Performance modeling; Program characteristics; Resource demands

Indexed keywords

ANALYTICAL MODELS; COMPUTER AIDED DESIGN; EFFICIENCY;

CHIP MULTIPROCESSOR; HARDWARE RESOURCES; MODEL PROGRAMS; MULTI-RESOURCE; PERFORMANCE MODELING; PROGRAM CHARACTERISTIC; QUALITY-OF-SERVICE; RESOURCE DEMANDS; RESOURCES BASED; SYSTEM EFFICIENCY;

QUALITY OF SERVICE;

EID: 79960159141     PISSN: 01635999     EISSN: None     Source Type: Journal    
DOI: 10.1145/2007116.2007118     Document Type: Conference Paper

References (25)

1. SPEC cpu2006 benchmark suite. In http://www.spec.org.
2. T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. Computer, 35:59-67, February 2002.
3. R. Bitirgen, E. Ipek, and J. F. Martinez. Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. In MICRO'41, pages 318-329, 2008.
4. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In ISCA'00, pages 83-94, 2000.
5. A. S. Dhodapkar and J. E. Smith. Managing multi-configuration hardware via dynamic working set analysis. In ISCA'02, pages 233-244, 2002. (Pubitemid 34691865)
6. S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith. A performance counter architecture for computing accurate cpi components. In ASPLOS-XII, pages 175-184, 2006.
7. S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith. A mechanistic performance model for superscalar out-of-order processors. ACM Trans. Comput. Syst., 27(2):1-37, 2009.
8. F. Guo, Y. Solihin, L. Zhao, and R. Iyer. A framework for providing quality of service in chip multi-processors. In MICRO'40, pages 343-355, 2007.
9. G. Hamerly, E. Perelman, J. Lau, and B. Calder. Simpoint 3.0: Faster and more flexible program analysis. In Journal of Instruction Level Parallelism, volume 7, pages 1-28, 2005.
10. M. Haungs, P. Sallee, and M. Farrens. Branch transition rate: a new metric for improved branch classification analysis. In HPCA'00, pages 241 -250, 2000. (Pubitemid 34197764)
11. E. Ïpek, S. A. McKee, R. Caruana, B. R. de Supinski, and M. Schulz. Efficiently exploring architectural design spaces via predictive modeling. In ASPLOS-XII, pages 195-206, 2006.
12. P. Joseph, K. Vaswani, and M. Thazhuthaveetil. Construction and use of linear regression models for processor performance analysis. In HPCA'06, pages 99 - 108, 2006. (Pubitemid 44418381)
13. N. Kapadia, J. Fortes, and C. Brodley. Predictive application-performance modeling in a computational grid environment. In Proceedings of The Eighth International Symposium on High Performance Distributed Computing, pages 47 -54, 1999. (Pubitemid 30502688)
14. T. S. Karkhanis and J. E. Smith. A first-order superscalar processor model. In ISCA'04, pages 338-349, 2004.
15. T. S. Karkhanis and J. E. Smith. Automated design of application specific superscalar processors: an analytical approach. In ISCA'07, pages 402-411, 2007. (Pubitemid 47591584)
16. D. Kaseridis, J. Stuecheli, J. Chen, and L. John. A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large cmp systems. In HPCA'10, pages 1-11, 2010.
17. R. Kumar, D. M. Tullsen, and N. P. Jouppi. Core architecture optimization for heterogeneous chip multiprocessors. In PACT'06, pages 23-32, 2006. (Pubitemid 46601078)
18. B. Lee and D. Brooks. Illustrative design space studies with microarchitectural regression models. In HPCA'07, pages 340 -351, 2007. (Pubitemid 47208178)
19. B. C. Lee and D. Brooks. Efficiency trends and limits from comprehensive microarchitectural adaptivity. In ASPLOS XIII, pages 36-47, 2008. (Pubitemid 351585392)
20. R. L. Mattson, D. R. Slutz, and I. L. Traiger. Evaluation techniques for storage hierarchies. IBM Syst. J., 9(2):78-117, 1970.
21. D. Narayanan and M. Satyanarayanan. Predictive resource management for wearable computing. In Proceedings of the 1st international conference on Mobile systems, applications and services, MobiSys'03, pages 113-128. ACM, 2003.
22. K. J. Nesbit, J. Laudon, and J. E. Smith. Virtual private caches. In ISCA'07, pages 57-68, 2007. (Pubitemid 47582091)
23. M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO'06, pages 423-432, 2006. (Pubitemid 351337015)
24. S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi. Cacti 5.1. HP Technical Reports, 2008.
25. T.-Y. Yeh and Y. N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In ISCA'93, pages 257-266, 1993.