0.5V bit-line-voltage self-boost-programming in ferroelectric-NAND flash memory

2011 3rd IEEE International Memory Workshop, IMW 2011

Volumn , Issue , 2011, Pages

  Zhang, Xizhen ^a   Miyaji, Kousuke ^b   Takahashi, Mitsue ^a   Takeuchi, Ken ^b   Sakai, Shigeki ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

Fe NAND; FeFET; Self Boost Program

Indexed keywords

BIT LINES; FE-NAND; FEFET; FLOATING GATES; LOWER-POWER CONSUMPTION; MEMORY CELL ARRAYS; SELF-BOOST PROGRAM;

FERROELECTRICITY; MEMORY ARCHITECTURE; NAND CIRCUITS;

FLASH MEMORY;

EID: 79959984935     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2011.5873233     Document Type: Article

References (12)

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