Experimental and simulated dc degradation of GaN HEMTs by means of gate-drain and gate-source reverse bias stress

Microelectronics Reliability

Volumn 50, Issue 9-11, 2010, Pages 1523-1527

  Di Lecce, Valerio ^a   Esposto, Michele ^a   Bonaiuti, Matteo ^a   Meneghesso, Gaudenzio ^b   Zanoni, Enrico ^b   Fantini, Fausto ^a   Chini, Alessandro ^a  

^a UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^b UNIVERSITY OF PADOVA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ACCEPTOR TRAPS; ALGAN LAYERS; ALGAN/GAN; DC STRESS; DRAIN TERMINALS; GAN HEMTS; GATE DRAIN; HORIZONTAL ELECTRIC FIELDS; NUMERICAL SIMULATION; OUTPUT CONDUCTANCE; REVERSE BIAS; SATURATED DRAIN CURRENTS; SOURCE JUNCTIONS; SOURCE TERMINAL;

DEGRADATION; DRAIN CURRENT; ELECTRIC FIELDS; ELECTRON MOBILITY; GALLIUM NITRIDE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 79959466819     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.07.126     Document Type: Conference Paper

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