Exploration of 3D stacked L2 cache design for high performance and efficient thermal control

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 295-298

  Sun, Guangyu ^a   Wu, Xiaoxia ^a   Xie, Yuan ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

3D; L2 caches; Performance; Thermal control

Indexed keywords

DESIGN OPTION; EVALUATION RESULTS; EXTRA DIMENSIONS; HIGH BANDWIDTH; L2 CACHE; MULTI-PROCESSORS; ON CHIP MEMORY; PEAK TEMPERATURES; SET-ASSOCIATIVE; THERMAL CONTROL; THERMAL MANAGEMENT; THREE DIMENSIONAL (3D) INTEGRATION;

DESIGN; LOW POWER ELECTRONICS; POWER ELECTRONICS; STRUCTURES (BUILT OBJECTS); TEMPERATURE CONTROL; THREE DIMENSIONAL;

CACHE MEMORY;

EID: 70449715692     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594306     Document Type: Conference Paper

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