Low-power CMOS equalizer design for 20-Gb/s systems

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 6, 2011, Pages 1321-1336

  Ibrahim, Sameh ^a   Razavi, Behzad ^b  

^a MARVELL SEMICONDUCTOR INC   (United States)

^b Engineering IV   (United States)

Author keywords

Bit error rate; CML latch; decision feedback equalizers; high speed equalizers; latch offset; latch sensitivity; unrolled DFE

Indexed keywords

CML LATCH; HIGH-SPEED EQUALIZERS; LATCH OFFSET; LATCH SENSITIVITY; UNROLLED DFE;

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; OPTICAL COMMUNICATION;

DECISION FEEDBACK EQUALIZERS;

EID: 79957660442     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2134450     Document Type: Article

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