A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 889-896

  Emami Neyestanak, Azita ^a,b   Varzaghani, Aida ^c   Bulzacchelli, John F ^a,d   Rylyakov, Alexander ^d   Yang, Chih Kong Ken ^a,c   Friedman, Daniel J ^a,d  

^a IEEE   (United States)

^b Columbia University ^*  (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Decision feedback equalization (DFE); Interconnects; Loop unrolling; Receiver; Summation; Switched capacitors

Indexed keywords

CLOCK BUFFERS; FRONT-END SAMPLE-HOLD CIRCUITS; POWER RECEIVERS;

BUFFER CIRCUITS; CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; INTERCONNECTION NETWORKS; MULTIPLEXING;

DECISION FEEDBACK EQUALIZERS;

EID: 33947669913     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.892156     Document Type: Article

References (11)

1. V. Stojanovic, A. Ho, B. Garlepp, F. Chen, J. Wei, E. Alon, C. Werner, J. Zerbe, and M. A. Horowitz, "Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver," in Symp. VLSI Circuits 2004 Dig. Tech. Papers, 2004, pp. 348-351.
2. T. Beukema, M. Sorna, K. Selander, S. Zier, B. L. Ji, P. Murfet, J. Mason, W. Rhee, H. Ainspan, B. Parker, and M. Beakes, "A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2633-2645, Dec. 2005.
3. R. Payne, P. Landman, B. Bhakta, S. Ramaswamy, S. Wu, J. D. Powers, M. U. Erdogan, A.-L. Yee, R. Gu, L. Wu, Y. Xie, B. Parthasarathy, K. Brouse, W. Mohammed, K. Heragu, V. Gupta, L. Dyson, and W. Lee, "A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2646-2657, Dec. 2005.
4. K. Krishna, D. A. Yokoyama-Martin, S. Wolfer, C. Jones, M. Loikkanen, J. Parker, R. Segelken, J. L. Sonntag, J. Stonick, S. Titus, and D. Weinlader, "A 0.6 to 9.6 Gb/s binary backplane transceiever core in 0.13 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 64-65.
5. A. Varzaghani and C.-K. K. Yang, "A 6-GSamples/s multi-level decision-feedback-equalizer embedded in a 4-bit time-interleaved pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 935-944, Apr. 2006.
6. M. Callicotte, J. Little, H. Takatori, K. Dyer, and C.-H. Lee, "A 12.5 Gb/s single-chip transceiver for UTP cables in 0.13 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 86-87.
7. R. Farjad-Rad, C.-K. K. Yang, and M. Horowitz, "A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 757-764, May 2000.
8. A. Fiedler et al., "A 1.0625 Gb/s transceiver with 2X oversampling and transmit pre-emphasis," in IEEE ISSCC Dig. Tech. Papers, 1997, pp. 238-239.
9. S. Kasturia and J. H. Winters, "Techniques for high-speed implementation of nonlinear cancellation," IEEE J. Sel. Areas Commun., vol. 9, no. 6, pp. 711-717, Jun. 1991.
10. G. M. Haller and B. A. Wooley, "A 700-MHz switched-capacitor analog waveform sampling circuit," IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 500-508, Apr. 1994.
11. S.-J. Bae, H.-J. Chi, Y.-S. Sohn, and H.-J. Park, "A 2 Gb/s 2-tap DFE receiver for multi-drop single-ended signaling systems with reduced noise," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 244-245.