A 20Gb/s 40mW equalizer in 90nm CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 170-171

  Ibrahim, Sameh A ^a   Razavi, Behzad ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

20 GB/S; 90NM CMOS; BACKPLANES; CHANNEL FREQUENCY RESPONSE; CIRCUIT BOARDS; CIRCUIT DESIGNS; DATA RATES; FR-4 BOARDS; I/O VOLTAGE; IMPEDANCE DISCONTINUITIES; LINEAR EQUALIZATION; OUTPUT DRIVERS; PARALLEL CHANNEL; PIN COUNTS; PRACTICAL SYSTEMS; SERIAL LINK; SYSTEM DESIGN;

AMPLIFICATION; CMOS INTEGRATED CIRCUITS; FREQUENCY RESPONSE; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; TRANSMITTERS;

EQUALIZERS;

EID: 77952224798     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433999     Document Type: Conference Paper

References (6)

1. K. Sunaga et al., "An 18Gb/s Duobinary Receiver with a CDR-assisted DFE," ISSCC Dig.Tech. Papers, pp. 274-275, Feb. 2009.
2. D. Z. Turker et al., "A 19Gb/s 38mW 1-Tap Speculative DFE receiver in 90nm CMOS," IEEE Symp. VLSI Circuits, pp. 216-217, Jun. 2009.
3. H. Wang et al., "A 21-Gb/s 87-mW Transceiver with FFE/DFE/Linear Equalizer in 65-nm CMOS Technology," IEEE Symp. VLSI Circuits, pp. 50-51, Jun. 2009.
4. J. F. Bulzacchelli et al., "A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology," IEEE J. Solid-State Circuits, vol. 41, pp. 2885-2900, Dec. 2006.
5. S. Gondi and B. Razavi, "Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial Link Receivers," IEEE J. Solid-State Circuits, vol. 42, pp. 1999-2011, Sep. 2007.
6. J. Lee and B. Razavi, "A 40-Gb/s Clock and Data Recovery Circuit in 0.18-μm CMOS Technology," IEEE J. Solid-State Circuits, vol. 38, pp. 2181-2190, Dec. 2003.