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Volumn 41, Issue 10, 2006, Pages 2224-2232

A 1-tap 40-Gb/s look-Ahead decision feedback equalizer in 0.18-μm SiGe BiCMOS technology

Author keywords

40 Gb s; Decision feedback equalizer; SiGe BiCMOS

Indexed keywords

40 GB/S; ANALOG DIFFERENTIAL VOLTAGE; SIGE BICMOS;

EID: 33749536071     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.878109     Document Type: Conference Paper
Times cited : (32)

References (18)
  • 1
    • 2442503444 scopus 로고    scopus 로고
    • Adaptive PMD compensation by electrical and optical techniques
    • Apr.
    • F. Buchali and H. Bülow, "Adaptive PMD compensation by electrical and optical techniques," J. Lightw. Technol., vol. 22, no. 4, pp. 1116-1126, Apr. 2004.
    • (2004) J. Lightw. Technol. , vol.22 , Issue.4 , pp. 1116-1126
    • Buchali, F.1    Bülow, H.2
  • 2
    • 67649099942 scopus 로고    scopus 로고
    • A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems
    • May
    • J. Sewter and A. Chan Carusone, "A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May 2005, pp. 1521-1524.
    • (2005) Proc. IEEE Int. Symp. Circuits and Systems (ISCAS) , pp. 1521-1524
    • Sewter, J.1    Carusone, A.C.2
  • 3
    • 33746884699 scopus 로고    scopus 로고
    • A 3-tap FIR filter with cascaded distributed tap amplifiers for equalization up to 40 Gb/s in 0.18-μm CMOS
    • Aug.
    • J. Sewter and A. Chan Carusone, "A 3-tap FIR filter with cascaded distributed tap amplifiers for equalization up to 40 Gb/s in 0.18-μm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1919-1929, Aug. 2006.
    • (2006) IEEE J. Solid-state Circuits , vol.41 , Issue.8 , pp. 1919-1929
    • Sewter, J.1    Carusone, A.C.2
  • 4
    • 21644443524 scopus 로고    scopus 로고
    • A 49-Gb/s, 7-tap transversal filter in 0.18-μm SiGe BiCMOS for backplane equalization
    • Oct.
    • A. Hazneci and S. P. Voinigescu, "A 49-Gb/s, 7-Tap transversal filter in 0.18-μm SiGe BiCMOS for backplane equalization," in IEEE CSIC Dig., Oct. 2004, pp. 101-104.
    • (2004) IEEE CSIC Dig. , pp. 101-104
    • Hazneci, A.1    Voinigescu, S.P.2
  • 6
    • 0343526899 scopus 로고    scopus 로고
    • PMD mitigation at 10 Gb/s using linear and nonlinear integrated electronic equalizer circuits
    • H. Bülow, F. Buchali, W. Baumert, R. Ballentin, and T. Wehren, "PMD mitigation at 10 Gb/s using linear and nonlinear integrated electronic equalizer circuits," Electron. Lett., vol. 36, no. 2, pp. 163-164, 2000.
    • (2000) Electron. Lett. , vol.36 , Issue.2 , pp. 163-164
    • Bülow, H.1    Buchali, F.2    Baumert, W.3    Ballentin, R.4    Wehren, T.5
  • 7
    • 31744444943 scopus 로고    scopus 로고
    • A 10 Gb/s equalizer with integrated clock and data recovery for optical communication systems
    • Sep.
    • D. McPherson, H. Tran, and P. Popescu, "A 10 Gb/s equalizer with integrated clock and data recovery for optical communication systems," Int. J. High Speed Electron. Syst., vol. 15, no. 3, pp. 525-548, Sep. 2005.
    • (2005) Int. J. High Speed Electron. Syst. , vol.15 , Issue.3 , pp. 525-548
    • McPherson, D.1    Tran, H.2    Popescu, P.3
  • 10
    • 0026171346 scopus 로고
    • Techniques for high-speed implementation of nonlinear cancellation
    • Jun.
    • S. Kasturia and J. H. Winters, "Techniques for high-speed implementation of nonlinear cancellation," IEEE J. Sel. Areas Commun., vol. 9, no. 5, pp. 711-717, Jun. 1991.
    • (1991) IEEE J. Sel. Areas Commun. , vol.9 , Issue.5 , pp. 711-717
    • Kasturia, S.1    Winters, J.H.2
  • 11
    • 0031103014 scopus 로고    scopus 로고
    • A mixed-signal decision-feedback equalizer that uses a look-ahead architecture
    • Mar.
    • R. S. Kajley, P. J. Hurst, and J. E. C. Brown, "A mixed-signal decision-feedback equalizer that uses a look-ahead architecture," IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 450-459, Mar. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , Issue.3 , pp. 450-459
    • Kajley, R.S.1    Hurst, P.J.2    Brown, J.E.C.3
  • 13
    • 0347566262 scopus 로고    scopus 로고
    • 6 kΩ, 43 Gb/s differential transimpedance-limiting amplifier with autozero feedback and high dynamic range
    • H. Tran, F. Pera, D. S. McPherson, D. Viorel, and S. P. Voinigescu, "6 kΩ, 43 Gb/s differential transimpedance-limiting amplifier with autozero feedback and high dynamic range," in IEEE GaAs IC Symp. Tech. Dig., 2003, pp. 241-244.
    • (2003) IEEE GaAs IC Symp. Tech. Dig. , pp. 241-244
    • Tran, H.1    Pera, F.2    McPherson, D.S.3    Viorel, D.4    Voinigescu, S.P.5
  • 15
    • 0030213937 scopus 로고    scopus 로고
    • Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s
    • Aug.
    • H. Rein and M. Moller, "Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s," IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1076-1090, Aug. 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.31 , Issue.8 , pp. 1076-1090
    • Rein, H.1    Moller, M.2
  • 16
    • 0025419648 scopus 로고
    • Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits
    • Apr.
    • W. Fang, "Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 572-583, Apr. 1990.
    • (1990) IEEE J. Solid-state Circuits , vol.25 , Issue.2 , pp. 572-583
    • Fang, W.1
  • 17
    • 18444371091 scopus 로고    scopus 로고
    • Design analysis and circuit enhancements for high-speed bipolar flip-flops
    • May
    • T. E. Collins, V. Manan, and S. I. Long, "Design analysis and circuit enhancements for high-speed bipolar flip-flops," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1166-1174, May 2005.
    • (2005) IEEE J. Solid-state Circuits , vol.40 , Issue.5 , pp. 1166-1174
    • Collins, T.E.1    Manan, V.2    Long, S.I.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.