A 19gb/s 38mW 1-tap speculative DFE receiver in 90nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 216-217

  Turker, Didem Z ^a   Rylyakov, Alexander ^b   Friedman, Daniel ^b   Gowda, Sudhir ^b   Sánchez Sinencio, Edgar ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

DFE; Half rate sampling; ISI; Speculation

Indexed keywords

90NM CMOS; AT-SPEED; CHANNEL INPUTS; DATA STREAM; DECISION THRESHOLD; DFE; HALF-RATE; HALF-RATE SAMPLING; INPUT LATCH; ISI; ISI CANCELLATION; SPECULATION;

INTERSYMBOL INTERFERENCE;

VLSI CIRCUITS;

EID: 70449435111     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A. Rylyakov, "An 11Gb/s 2.4mW Half-Rate Sampling 2-Tap DFE Receiver in 65nm CMOS", Symp. VLSI Circuits, pp.272-273, June 2007.
2. M. Park, et al., "A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver," ISSCC Dig. Tech. Papers, pp. 230-231, Feb. 2007.
3. V. Stojanovic, et. al, "Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equalization and Data Recovery," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, April 2005.
4. A. Garg, A. Carusone, S. Voinigescu, "A 1-Tap 40-Gbps Look-ahead Decision Feedback Equalizer in 0.18m SiGe BiCMOS Technology", IEEE J. Solid-State Circuits, vol. 41, pp. 2224-2232, Oct. 2006.