Threshold testing: Covering bridging and other realistic faults

Proceedings of the Asian Test Symposium

Volumn 2005, Issue , 2005, Pages 390-395

  Jiang, Zhigang ^a   Gupta, Sandeep K ^b  

^a SYNTEST TECHNOLOGIES INC   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATOR (ATPG); REALISTIC FAULTS; THRESHOLD TESTING;

AUTOMATIC TESTING; COST EFFECTIVENESS; MATHEMATICAL MODELS; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 33846931865     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2005.108     Document Type: Conference Paper

References (5)

1. H. Chung and A. Ortega, "System Level Fault Tolerance for Motion Estimation", Technical Report USC-SIPI #354, Department of Electrical Engineering-system, University of Southern California, Los Angeles, CA, 2002
2. Z. Jiang and S. Gupta, "An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes," Proc. International Test Conference, pp.824-833, 2002
3. R. C. Leachman and C. N. Berglund, "Systematic Mechanisms Limited Yield (SMLY) Assessment Study", International SEMATECH, Doc. #03034383A-ENG, March 2003
4. M. J. Y. Williams and J. B. Angel, "Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional logic," IEEE Trans. On Computers, Vol. C-22, No.1, pp.46-60, January, 1973
5. S. Ma, I. Shaik, R. S. Fetherston, "A Comparison of Bridging Fault Simulation Methods", In Proc. Int. Test Conference, pp.587-595, 1999