Redundancy removal and simplification of combinational circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn 1992-April, Issue , 1992, Pages 268-273

  Menon, P R ^a   Ahuja, H ^a  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TESTING; TIMING CIRCUITS; VLSI CIRCUITS;

BENCHMARK CIRCUIT; DETECTABILITY; FAN-OUT; RE CONVERGENCES; REDUNDANCY REMOVAL; TEST GENERATIONS;

REDUNDANCY;

EID: 84941363915     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.1992.232764     Document Type: Conference Paper

References (15)

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