Sequential logic optimization by redundancy addition and removal

Volumn , Issue , 1993, Pages 310-315

  Entrena, Luis ^a   Cheng, Kwang Ting ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; COMBINATORIAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; ITERATIVE METHODS; LOGIC DESIGN; MINIMIZATION OF SWITCHING NETS; OPTIMIZATION; REDUNDANCY; STATE ASSIGNMENT;

REDUNDANCY ADDITION AND REMOVAL; SEQUENTIAL LOGIC OPTIMIZATION;

SEQUENTIAL CIRCUITS;

EID: 0027867675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)