Applications of high-capacity crossbar memories in cryptography

IEEE Transactions on Nanotechnology

Volumn 10, Issue 3, 2011, Pages 489-498

  Rührmair, Ulrich ^a   Jaeger, Christian ^b   Bator, Matthias ^b,c   Stutzmann, Martin ^b   Lugli, Paolo ^a   Csaba, Gyrgy ^a,d  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b WALTER SCHOTTKY INSTITUT   (Germany)

^c PAUL SCHERRER INSTITUTE   (Switzerland)

^d UNIVERSITY OF NOTRE DAME   (United States)

Author keywords

Crossbar memories; nonvolatile memories; physical cryptography; physical unclonable function (PUF)

Indexed keywords

CIRCUIT-LEVEL SIMULATION; CROSS-BAR MEMORIES; CROSSBAR ARRAYS; EXPERIMENTAL DATA; FEASIBILITY STUDIES; HIGH-CAPACITY; INFORMATION CONTENTS; NEW DESIGN; NONVOLATILE MEMORIES; PHYSICAL ATTACKS; PHYSICAL CRYPTOGRAPHY; PHYSICAL UNCLONABLE FUNCTION (PUF); PHYSICAL UNCLONABLE FUNCTIONS; READOUT RATE; SENSITIVE INFORMATIONS; TIME-PERIODS;

ACCESS CONTROL;

CRYPTOGRAPHY;

EID: 79955919867     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2010.2049367     Document Type: Article

References (32)

1. R. Pappu, B. Recht, J. Taylor, and N. Gershenfeld, "Physical One-Way functions," Science, vol. 297, no. 5589, pp. 2026-2030, Sep. 2002.
2. D. B. Gassend, D. Clarke, M. Van Dijky, and S. Devadas, "Silicon physical random functions," presented at the CSC, Washington, DC, Nov. 18-22 2002.
3. D. Lim, J. W. Lee, B. Gassend, G. E. Suh, M. Van Dijk, and S. Devadas, "Extracting secret keys from integrated circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 10, pp. 1200-1205, Oct. 2005. (Pubitemid 43131686)
4. D. Lim, "Extracting secret keys from integrated circuits," M.Sc. dissertation, MIT, Cambridge, MA, 2004.
5. B. Gassend, D. Lim, D. Clarke, M. Van Dijk, and S. Devadas, "Identification and authentication of integrated circuits," Concurrency Comput., Pract. Exp., vol. 16, no. 11, pp. 1077-1098, 2004.
6. U. Rührmair, J. Sölter, and F. Sehnke. (2009). On the foundations of physical unclonable functions, Cryptology ePrint Archive: Rep. 2009/277. Available: http://eprint.iacr.org/2009/277
7. U. Rührmair,F.Sehnke,J.Sölter, G. Dror, S. Devadas, and J. Schmidhuber, "Modeling attacks on physical unclonable functions," Cryptology ePrint Archive, Rep. 2010/251, 2010. Available: http://eprint.iacr. org/
8. J. Guajardo, S. S. Kumar, G. J. Schrijen, and P. Tuyls, "FPGA intrinsic PUFs and their use for IP protection," in Proc. 9th Int. Workshop CHES 2007 (LCNS), vol. 4727, New York: Springer-Verlag.
9. S. Maeda, H. Kuriyama, T. Ipposhi, S. Maegawa, Y. Inoue, M. Inuishi, N. Kotani, and T. Nishimura, "An artificial fingerprint device (AFD): A study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs," IEEE Trans. Electron Devices, vol. 50, no. 6, pp. 1451-1458, Jun. 2003.
10. S. Maeda, H. Kuriyama, T. Ipposhi, S. Maegawa, and M. Inuishi, "An artificial fingerprint device (AFD) module using poly-Si thin film transistors with logic LSI compatible process for built-in security," in Proc. IEDM Tech. Dig. Int. Electron Devices Meeting, 2001, pp. 34.5-1- 34.5-4.
11. R. Anderson, M. Bond, J. Clulow, and S. Skorobogatov, "Cryptographic processors-A survey," Proc. IEEE, vol. 94, no. 2, pp. 357-369, Feb. 2006.
12. S. S. Kumar, J. Guajardo, R. Maes, G.-J. Schrijen, and P. Tuyls, "The butterfly PUF protecting IP on every FPGA," in Proc. IEEE Int. Workshop Hardware-Oriented Secur. Trust (HOST 2008), Jun., pp. 67-70.
13. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, pp. 80-83, May 2008. (Pubitemid 351630336)
14. G. Snider, "Computing with hysteretic resistor crossbars," Appl. Phys. A, vol. 80, pp. 1165-1172, 2005. (Pubitemid 40454134)
15. G. F. Cerofolini, G. Arena, C. M. Camalleri, C. Galati, S. Reina, L. Renna, and D. Mascolo, "A hybrid approach to nanoelectronics," Nanotechnol-ogy, vol. 16, pp. 1040-1047, 2005. (Pubitemid 40878596)
16. A. DeHon, S. C. Goldstein, P. J. Kuekes, and P. Lincoln, "Nonphotolitho-graphic nanoscale memory density prospects," IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 215-228, Mar. 2005. (Pubitemid 40421657)
17. R. Beckman, E. Johnston-Halperin, Y. Luo, J. E. Green, and J. R. Heath, "Bridging dimensions: Demultiplexing ultrahigh-density nanowire circuits," Science, vol. 310, pp. 465-228, Oct. 21, 2005.
18. D. B. Strukov and K. K. Likharev, "Defect-tolerant architectures for nano-electronic crossbar memories," J. Nanosci. Nanotechnol., vol. 7, pp. 151- 167, 2007.
19. S. K. Dey and R. Zuleeg, "Processing and parameters of sol-gel PZT thin-films for GaAs memory applications," Ferroeloectrics, vol. 112, pp. 309-319, 1990.
20. P. Nangle, "Programming method for non-volatile memory," U.S. Patent 7106622, Sep. 12, 2006.
21. S. D. Brotherton, "Polycrystalline silicon thin film transistors," Semicond. Sci. Technol., vol. 10, pp. 721-738, 1995.
22. T. Antesberger, C. Jaeger, M. Scholz, and M. Stutzmann, "Structural and electronic properties of ultrathin polycrystalline Si layers on glass preparedbyaluminum-induced layer exchange," Appl. Phys. Lett., vol. 91, pp. 201909-1-201909-3, 2007. DOI: 10.1063/1.2803072. (Pubitemid 350128883)
23. C. Jaeger, T. Antesberger, and M. Stutzmann, "Hydrogen passivation of ultra-thin low-temperature polycrystalline silicon films for electronic applications," J. Non-Cryst. Solids, vol. 354, no. 19-25, pp. 2314-2318, May 2008. DOI: 10.1016/j.jnoncrysol.2007.09.040.
24. O. Nast, T. Puzzer, L. M. Koschier, A. B. Sproul, and S. R. Wenham, "Aluminum-induced crystallization of amorphous silicon on glass substrates above and below the eutectic temperature," Appl. Phys. Lett., vol. 73, pp. 3214-3216, 1998. (Pubitemid 128677358)
25. 2/amorphous Si structure," Jpn. J. Appl. Phys., vol. 35, pp. 2052-2056, 1996.
26. C. de Graaf, P. H. Woerlee, C. M. Hart, H. Lifka, P. W. H. de Vreede, P. J. M. Janssen, F. J. Sluijs, and G. M. Paulzen, "A novel high-density low-cost diode programmable read only memory," in Proc. Int. Electron Devices Meeting, Dec. 8-11, 1996, pp. 189-192.
27. M. Johnson, A. Al-Shamma, D. Bosch, M. Crowley, M. Farmwald, L. Fasoli, A. Ilkbahar, B. Kleveland, T. Lee, T.-Y. Liu, Q. Nguyen, R. Scheuerlein, K. So, and T. Thorp, "512-Mb PROM with a three-dimensional array of diode/antifuse memory cells," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1920-1928, Nov. 2003.
28. G. Csaba and P. Lugli, "Read-out design rules for molecular cross bar architectures," IEEE Trans. Nanotechnol., vol. 8, no. 3, pp. 369-374, May 2009.
29. M. Pra, G. Csaba, C. Erlen, and P. Lugli, "Simulation of ZnO diodes for application in non-volatile crossbar memories," J. Comput. Electron., vol. 7, no. 3, pp. 146-150, Sep. 2008.
30. P. Tuyls, G.-J. Schrijen, B. Skoric, J. Van Geloven, N. Verhaegh, and R. Wolters, "Read-proof hardware from protective coatings," in Proc. CHES 2006, pp. 369-383. (Pubitemid 44700070)
31. R. Janssen, A. Janotta, D. Dimova-Malinovska, and M. Stutzmann, "Optical and electrical properties of doped amorphous silicon suboxides," Phys. Rev. B, vol. 60, pp. 13561-13572, 1999.
32. C. Jaeger, M. Algasinger, U. Rührmair, G. Csaba, and M. Stutzmann, "Random pn-junctions for physical cryptography," Appl. Phys. Lett., vol. 96, 172103, 2010. DOI: 10.1063/1.3396186.